Alejandro X Levander

20130126892, May 23, 2013

May 18, 2012

13/475420

Kin Man Yu - Lafayette CA, US
Wladyslaw Walukiewicz - Kensington CA, US
Alejandro X. Levander - Berkeley CA, US
Sergei V. Novikov - Nottingham, GB
C. Thomas Foxon - Nottingham, GB

THE REGENTS OF THE UNIVERSITY OF CALIFORNIA - Oakland CA

H01L 29/20
H01L 21/04

257 76, 438513, 252512, 428220

A new composition of matter is described, amorphous GaNAs:Mg, wherein 0

20230062202, Mar 2, 2023

May 26, 2022

17/825367

- Cupertino CA, US
Baris Cagdaser - Sunnyvale CA, US
Patrick B Bennett - San Leandro CA, US
Michael Slootsky - Santa Clara CA, US
Alejandro X Levander - El Granada CA, US
Henry C Jen - Los Altos CA, US

G09G 3/20

An electronic device may have a display. The display may include an array of pixels formed on a silicon substrate. Display driver circuitry may be formed in a display driver integrated circuit that outputs display data and other control signals for operating the display. An interposer structure may be included in the electronic device. The interposer structure may be attached to the silicon display substrate and may only partially overlap the silicon display substrate. The display driver integrated circuit may be attached to the interposer structure and provide signals to the display pixels through the interposer structure. In another possible arrangement, the display driver integrated circuit may bridge a gap between the silicon display substrate and the flexible printed circuit. The display driver integrated circuit only partially overlaps the silicon display substrate in this arrangement.

20190019904, Jan 17, 2019

Sep 17, 2018

16/133477

- San Jose CA, US
Alejandro Levander - El Granada CA, US
Peter John Cousins - Los Altos CA, US

H01L 31/0236
H01L 31/068
H01L 31/18
H01L 31/047
H01L 31/0224
H01L 31/0216

Solar cell fabrication using laser patterning of ion-implanted etch-resistant layers, and the resulting solar cells, are described. In an example, a back contact solar cell includes an N-type single crystalline silicon substrate having a light-receiving surface and a back surface. Alternating continuous N-type emitter regions and segmented P-type emitter regions are disposed on the back surface of the N-type single crystalline silicon substrate, with gaps between segments of the segmented P-type emitter regions. Trenches are included in the N-type single crystalline silicon substrate between the alternating continuous N-type emitter regions and segmented P-type emitter regions and in locations of the gaps between segments of the segmented P-type emitter regions. An approximately Gaussian distribution of P-type dopants is included in the N-type single crystalline silicon substrate below the segmented P-type emitter regions. A maximum concentration of the approximately Gaussian distribution of P-type dopants is approximately in the center of each of the segmented P-type emitter regions between first and second sides of each of the segmented P-type emitter regions. Substantially vertical P/N junctions are included in the N-type single crystalline silicon substrate at the trenches formed in locations of the gaps between segments of the segmented P-type emitter regions.

20170229565, Aug 10, 2017

Sep 9, 2014

15/329216

- SANTA CLARA CA, US
Sansaptak DASGUPTA - Hillsboro OR, US
Alejandro X. LEVANDER - Santa Clara CA, US
Patrick MORROW - Portland OR, US

H01L 29/778
H01L 29/423
H01L 29/66
H01L 29/20

A multi-gate high electron mobility transistor (HEMT) and its methods of formation are disclosed. The multi-gate HEMT includes a substrate and an adhesion layer on top of the substrate. A channel layer is disposed on top of the adhesion layer, and a first gate electrode is disposed on top of the channel layer. The first gate electrode has a first gate dielectric layer in between the first gate electrode and the channel layer. A second gate electrode is embedded within the substrate and beneath the channel layer. The second gate electrode has a second gate dielectric layer completely surrounding the second gate electrode. A pair of source and drain contacts are disposed on opposite sides of the first gate electrode.

20170179310, Jun 22, 2017

Dec 16, 2015

14/971846

Staffan Westerberg - Sunnyvale CA, US
Alejandro Levander - El Granada CA, US
Peter John Cousins - Los Altos CA, US

H01L 31/0236
H01L 31/18
H01L 31/0224
H01L 31/047
H01L 31/0216

Solar cell fabrication using laser patterning of ion-implanted etch-resistant layers, and the resulting solar cells, are described. In an example, a back contact solar cell includes an N-type single crystalline silicon substrate having a light-receiving surface and a back surface. Alternating continuous N-type emitter regions and segmented P-type emitter regions are disposed on the back surface of the N-type single crystalline silicon substrate, with gaps between segments of the segmented P-type emitter regions. Trenches are included in the N-type single crystalline silicon substrate between the alternating continuous N-type emitter regions and segmented P-type emitter regions and in locations of the gaps between segments of the segmented P-type emitter regions. An approximately Gaussian distribution of P-type dopants is included in the N-type single crystalline silicon substrate below the segmented P-type emitter regions. A maximum concentration of the approximately Gaussian distribution of P-type dopants is approximately in the center of each of the segmented P-type emitter regions between first and second sides of each of the segmented P-type emitter regions. Substantially vertical P/N junctions are included in the N-type single crystalline silicon substrate at the trenches formed in locations of the gaps between segments of the segmented P-type emitter regions.

20170077281, Mar 16, 2017

Jun 13, 2014

15/122627

- Santa Clara CA, US
Sansaptak DASGUPTA - Hillsboro OR, US
Alejandro X. LEVANDER - Santa Clara CA, US
Patrick MORROW - Portland OR, US

H01L 29/778
H01L 21/02
H01L 29/205
H01L 29/04
H01L 29/20
H01L 29/66
H01L 21/78

A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.

20150179664, Jun 25, 2015

Dec 24, 2013

14/139954

Alejandro X. Levander - Santa Clara CA, US
Kimin Jun - Hillsboro OR, US

H01L 27/12
H01L 21/311
H01L 21/3105
H01L 21/02
H01L 21/762
H01L 21/265

Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface. Each defect-free semiconductor island may have one or more crystalline faceted edges and, with its accompanying oxide structure, may provide a planar surface for integration. In some cases, a layer of a second, different semiconductor material may be heteroepitaxially grown over the handle wafer/substrate to fill areas around the transferred islands. In some other cases, the handle wafer/substrate itself may be homoepitaxially grown to fill areas around the transferred islands.