Albert E Cosand

6597303, Jul 22, 2003

Aug 16, 2001

09/931609

Albert E. Cosand - Agoura Hills CA

HRL Laboratories, LLC - Malibu CA

H03M 134

341165, 341155

A comparator comprises a cross-coupled regenerative latch, a circuit connected to the cross-coupled regenerative latch and a clocking circuit. The cross-coupled regenerative latch regenerates, during a latching mode, a signal which is indicative of a difference between two input signals. The circuit connected to the cross-coupled regenerative latch operates as a voltage follower during an acquisition mode and as a cascode amplifier stage during the latching mode. The clocking circuit switches the comparator from the acquisition mode to the latching mode and vice versa. The comparator eliminates the extraneous loading from the positive feedback when the regeneration takes place, so that a very fast regeneration time constant is obtained.

6628167, Sep 30, 2003

Oct 23, 2002

10/278956

Susan Morton - Newbury Park CA
Albert Cosand - Agoura Hills CA

The Boeing Company - Chicago IL

H03F 345

330252, 330251, 330 9, 327 97, 341155

A linearized folding amplifier circuit ( ) includes a comparator ( ) that has a first state and a second state, and a switched output circuit that has a pair of outputs. The non-linearity in the response of a differential transistor pair to an input signal is partially linearized by a first resistor connecting the emitters of the two input transistors. The input is further linearized in response to the first and second state-controlling pairs of transistors and a differential error voltage therebetween that is replicated from the differential error in the base-voltages emitter voltages of the input differential pair. The output of the circuit is the combination of the partially linearized portion from the first resistor and a linearized transconductor circuit that has an output formed in response to the differential error.

6628220, Sep 30, 2003

Jan 31, 2002

10/066011

Albert E. Cosand - Agoura Hills CA

Raytheon Company - Lexington MA

H03M 166

341144, 341119, 326126

A current switch circuit including a current switch including a first transistor and a second transistor connected as a differential pair and receiving a differential logic signal at their bases, and logic signal controlling circuitry coupled to the first and second transistors for offsetting a transition starting point of to differential logic signal to offset a self-heating induced shift in a switching threshold of the current switch.

6975682, Dec 13, 2005

Jun 12, 2001

09/879470

Albert E. Cosand - Agoura Hills CA, US

Raytheon Company - Waltham MA

H04B014/06

375247, 341200

A quantizer adapted for use with a delta-sigma analog-to-digital converter. The quantizer includes first and second comparators adapted to compare an input analog signal to a threshold and provide a digital output in response thereto. First and second thresholds are provided to the first and second comparators respectively. In accordance with the present teachings, a mechanism is provided for changing the thresholds to minimize conversion errors. While the mechanism for changing the thresholds may be implemented with resistive and/or capacitive ladders, in the illustrative embodiment, digital-to-analog converters are utilized. The DACs are driven by error shaping logic. The inventive quantizer allows for an improved delta-sigma analog-to-digital converter design which combines an ADC and a DAC. The DAC reconstructs the analog equivalent of the digital output of the ADC. The ADC is a flash converter consisting of one comparator per threshold.

6999019, Feb 14, 2006

Apr 8, 2004

10/821376

Albert E. Cosand - Agoura Hills CA, US

The Boeing Company - Chicago IL

H03M 1/12
H03M 1/00

341156, 341122

A subranging analog-to-digital converter (ADC) includes an integrating sample-and-hold circuit. The integrating sample-and-hold circuit is configured to sample an input voltage by charging at least one capacitor by coupling a current proportional to the input voltage to the at least one capacitor. A coarsely-quantizing ADC is configured to convert the voltage on the at least one capacitor to a digitized value. A digital-to-analog converter is configured to convert the digitized value to an analog voltage. A finely-quantizing ADC is configured to convert the difference between the analog voltage and the voltage on the charged at least one capacitor in the integrating sample-and-hold circuit to another digitized value.

7158062, Jan 2, 2007

Jan 21, 2004

10/761790

Albert E. Cosand - Agoura Hills CA, US

Raytheon Company - Waltham MA

H03M 3/00

341143, 341133, 341136

A switch having a first arrangement for providing a first set of first and second complementary intermediate signals; a second arrangement for providing a second set of third and fourth complementary intermediate signals; a third arrangement responsive to the first set of signals for providing complementary output signals; a fourth arrangement responsive to the second set of signals for providing complementary output signals; and a fifth arrangement for selectively activating the third means or the fourth arrangement in response to a control signal.

7349471, Mar 25, 2008

Nov 19, 2003

10/707076

Albert Cosand - Agoura Hills CA, US
Donald A. Hitko - Malibu CA, US
Michael Yung - Los Angeles CA, US

The Boeing Company - Chicago IL

H03K 7/04
H03K 7/06
H03K 9/04
H03K 9/06

375239, 375346, 375259

A communication receiver () includes a data receiver () that receives a pulse-position modulated signal (). A clock circuit () separates a reference clock signal () into multiple coordinating clock signals A, B, and C. Multiple time integrators () are gated to generate multiple time-integrated signals in response to the pulse-position modulated signal () and the coordinating clock signals A, B, and C. A combiner () forms a demodulated signal from the time-integrated signals IntA, IntB, and IntC.

7573305, Aug 11, 2009

Mar 3, 2008

12/041085

Albert E. Cosand - Agoura Hills CA, US
Susan Morton - Pittsford NY, US

HRL Laboratories, LLC - Malibu CA

H03B 19/00

327117, 327113, 327114, 327115, 327118

A high speed divider circuit is disclosed. The circuit contains a plurality of latches and buffers. The maximum input clock frequency of the divider circuit is increased over that implemented with only latches connected in a ring by feed forwarding the output of an early switching latch to the output of a later switching latch through buffers. The feed forward signal aids the later switching latch to complete the next state transition. By choosing the appropriate ratio of the buffer tail current to the latch tail current, the divider circuit can be made into a dynamic divider circuit.