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Alan Bryant Heirich

from Grass Valley, CA
Age ~63

Alan Heirich Phones & Addresses

  • Grass Valley, CA
  • Canyon Country, CA
  • Hurleyville, NY
  • 2024 Touraine Ln, Half Moon Bay, CA 94019 (650) 726-3919
  • Pasadena, CA
  • Ann Arbor, MI
  • Encinitas, CA
  • San Mateo, CA
  • 2024 Touraine Ln, Half Moon Bay, CA 94019 (650) 823-4123

Work

Company: Imagination technologies Position: Principal software engineer

Education

School / High School: Caltech 1998 Specialities: Philosophy

Skills

Algorithms • Distributed Systems • High Performance Computing • Computer Architecture • Multithreading • Opencl • Asic • Software Engineering • Image Processing • Kernel • Gpu • Opengl • C++ • Python • C • Debugging • Linux • Software Development • Computer Science • Parallel Computing • Computer Graphics • Gpgpu • Parallel Programming • Programming • Device Drivers • Software Design • Computer Vision • Android • Linux Kernel • Objective C • Embedded Systems • Scalability • Embedded Software • Compilers • Unix • System Architecture • Gnu Debugger • Perforce • Machine Learning • Object Oriented Design • X86 • Subversion • Processors • Arm • Git • Architectures • Early Stage Startups • Architecture • High Performance Computing

Emails

Industries

Computer Software

Resumes

Resumes

Alan Heirich Photo 1

Alan Heirich

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Location:
2024 Touraine Ln, Half Moon Bay, CA 94019
Industry:
Computer Software
Work:
Imagination Technologies
Principal Software Engineer

Apple
Engineer

Amd
Senior Member of Technical Staff

Stream Processors
Senior Dsp Software Engineer

Playstation
Staff Software Engineer
Education:
Caltech 1998
Caltech 1991 - 1997
Doctorates, Doctor of Philosophy
Caltech 1992
Caltech 1989 - 1991
Master of Science, Masters
Uc San Diego 1987 - 1989
Master of Science, Masters
University of Michigan 1985 - 1987
Bachelors, Bachelor of Arts
Skills:
Algorithms
Distributed Systems
High Performance Computing
Computer Architecture
Multithreading
Opencl
Asic
Software Engineering
Image Processing
Kernel
Gpu
Opengl
C++
Python
C
Debugging
Linux
Software Development
Computer Science
Parallel Computing
Computer Graphics
Gpgpu
Parallel Programming
Programming
Device Drivers
Software Design
Computer Vision
Android
Linux Kernel
Objective C
Embedded Systems
Scalability
Embedded Software
Compilers
Unix
System Architecture
Gnu Debugger
Perforce
Machine Learning
Object Oriented Design
X86
Subversion
Processors
Arm
Git
Architectures
Early Stage Startups
Architecture
High Performance Computing

Publications

Us Patents

First-Order Difference Compression For Interleaved Image Data In A High-Speed Image Compositor

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US Patent:
6516032, Feb 4, 2003
Filed:
Mar 8, 1999
Appl. No.:
09/264348
Inventors:
Alan Heirich - Half Moon Bay CA
Pankaj Mehra - San Jose CA
Robert W. Horst - Saratoga CA
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
H04B 166
US Classification:
37524017, 37524018
Abstract:
An encoder accepts an N byte set of values for each of a plurality of image components, with N being greater than one and, for each N byte set of values, identifies a compressed symbol length, K, wherein K is the smallest integer such that the difference between any two adjacent bytes is expressible in K bits or less, outputs an indication of K and outputs a K bit difference between the byte and an immediately prior byte, for each byte in the set.

Parallel Pipelined Merge Engines

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US Patent:
6753878, Jun 22, 2004
Filed:
Mar 8, 1999
Appl. No.:
09/264347
Inventors:
Alan Heirich - Half Moon Bay CA
Laurent Moll - Palo Alto CA
Mark Shand - Palo Alto CA
Albert Tam - Fremont CA
Robert W. Horst - Saratoga CA
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1516
US Classification:
345629, 345619, 345630, 345632, 345634
Abstract:
An image generator is organized into a plurality of rendering engines, each of which renders an image of a part scene and provides the part image to a merge engine associated with that rendering engine. The image is a part image in that it usually contains less than all of the objects in the image to be rendered. The merge engine merges the part image from its associated rendering engine with the part image provided by a prior merge engine and provides the merged part image to a next merge engine. One or more merge engines are designated the output merge engines and these output merge engines output a merged part image that is (a portion of) the ultimate output of the image generator, the full rendered image. Each merge engine performs its merge process on the pixels it has from its rendering engine and from its prior neighbor merge engine, in a pipelined manner and without necessarily waiting for all of the pixels of the part image or the merged part image.

Statistical Rendering Acceleration

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US Patent:
7289119, Oct 30, 2007
Filed:
May 10, 2005
Appl. No.:
11/126496
Inventors:
Alan Bryant Heirich - Foster City CA, US
Axel Mamode - Foster City CA, US
Assignee:
Sony Computer Entertainment Inc. - Tokyo
International Classification:
G06T 15/00
G06T 15/10
G06T 15/20
US Classification:
345427, 345619
Abstract:
Different rendering techniques are selected for portions of a scene based on statistical estimates of the portions' rendering costs. A scene is partitioned into a bounding volume hierarchy. Each bounding volume includes a statistical model of the spatial distribution of geometric primitives within the bounding volume. An image to be rendered is partitioned into screen regions and each screen region is associated with one or more bounding volumes and their statistical models. The associated statistical models of a screen region are evaluated to estimate the rendering cost, such as the probable number of geometric primitives per pixel, for the screen region. Based on the rendering cost, the screen region is assigned to a dense geometry renderer, such as a ray tracing renderer, or a sparse geometry renderer, such as a rasterization renderer. Rendered screen regions are combined to form a rendered image.

Interactive Debugging And Monitoring Of Shader Programs Executing On A Graphics Processor

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US Patent:
7548244, Jun 16, 2009
Filed:
Jan 12, 2005
Appl. No.:
11/035091
Inventors:
Alan Bryant Heirich - Foster City CA, US
Assignee:
Sony Computer Entertainment Inc. - Tokyo
International Classification:
G06F 15/00
G06T 1/00
G06F 15/16
G06F 15/80
US Classification:
345501, 345502, 345505
Abstract:
A development application leverages the programmability of shader execution units in the graphics processing subsystem to make graphics processing subsystem state data accessible to applications executed outside the graphics processing subsystem. The development application modifies shaders to include state output instructions adapted to direct a shader execution unit to copy graphics processing subsystem state data to a location in the computer system that is accessible to applications executed outside of the graphics processing subsystem. Following the execution of the state output instructions, the shader execution unit can be halted or can continue executing the shader. The development application can modify the shader to include state restoration instructions adapted to direct the shader execution unit to set state data of the graphics processing subsystem to previous or new values. The development application can dynamically modify shaders with state output and restoration instructions to update state data of the graphics processing subsystem.

Distributed Rendering Of Interactive Soft Shadows

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US Patent:
7714858, May 11, 2010
Filed:
Apr 18, 2003
Appl. No.:
10/418502
Inventors:
Michael A. Isard - San Francisco CA, US
Alan B. Heirich - Half Moon Bay CA, US
Mark A. Shand - Dampierre Yvellnes, FR
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06T 15/00
US Classification:
345426, 345419, 345423, 345428
Abstract:
The disclosed embodiments relate to a rendering cluster that renders an image of a scene object. The rendering cluster may comprise an illumination node that produces illumination output based on lighting properties of the scene object and a material node that produces material output based on material properties of the scene object. The illumination output is combined with the material output to form the image.

Cone-Culled Soft Shadows

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US Patent:
7755626, Jul 13, 2010
Filed:
May 3, 2006
Appl. No.:
11/418415
Inventors:
Louis Frederic Bavoil - Feucherolles, FR
Alan Bryant Heirich - Half Moon Bay CA, US
Assignee:
Sony Computer Entertainment Inc. - Tokyo
International Classification:
G06T 15/50
G06T 15/60
G06T 17/00
US Classification:
345426, 345419
Abstract:
Soft shadows in computer graphics images are created by rendering the scene from the camera viewpoint and at least one light viewpoint. The positions of scene fragments and light fragments in the scene are stored. For each scene fragment, a frustum is defined between the position of the scene fragment and the light source. Light fragments are evaluated with respect to the frustum to select light fragments blocking light between the light source and the scene fragment. A color or monochromatic shading value is determined for each scene fragment that indicates the amount of light blocked or transmitted by the light fragments. The shading values are then used to alter scene fragments accordingly. Computer graphics images with soft shadows can be created entirely by a graphics processing subsystem or by a graphics processing subsystem in conjunction with a central processing unit using a pipelined, deferred shading approach.

Technique For Processing A Computer Program

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US Patent:
7788635, Aug 31, 2010
Filed:
Jul 14, 2006
Appl. No.:
11/487532
Inventors:
Alan B. Heirich - Half Moon Bay CA, US
Assignee:
Sony Computer Entertainment Inc. - Tokyo
International Classification:
G06F 9/44
G06F 17/50
US Classification:
717104, 717105, 717153, 717144, 717151, 705 7, 705 8, 705 11
Abstract:
The present invention is directed to a method for processing, in a computer system, a computer program having a plurality of operations. The method features calling a dynamic programming routine to generate a schedule for executing a subgroup of the plurality of operations by modeling operations of a computational processor associated with the computer system to minimize a computational cost of placing the computer system in a final machine state (finMS).

Interactive Debugging And Monitoring Of Shader Programs Executing On A Graphics Processor

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US Patent:
7907143, Mar 15, 2011
Filed:
May 18, 2009
Appl. No.:
12/467796
Inventors:
Alan B. Heirich - Half Moon Bay CA, US
Assignee:
Sony Computer Entertainment Inc. - Tokyo
International Classification:
G06F 15/80
G06F 15/00
G06F 15/16
G06T 15/50
G06T 15/60
G06T 1/00
US Classification:
345505, 345426, 345501, 345502
Abstract:
A development application leverages the programmability of shader execution units in the graphics processing subsystem to make graphics processing subsystem state data accessible to applications executed outside the graphics processing subsystem. The development application modifies shaders to include state output instructions adapted to direct a shader execution unit to copy graphics processing subsystem state data to a location in the computer system that is accessible to applications executed outside of the graphics processing subsystem. Following the execution of the state output instructions, the shader execution unit can be halted or can continue executing the shader. The development application can modify the shader to include state restoration instructions adapted to direct the shader execution unit to set state data of the graphics processing subsystem to previous or new values. The development application can dynamically modify shaders with state output and restoration instructions to update state data of the graphics processing subsystem.
Alan Bryant Heirich from Grass Valley, CA, age ~63 Get Report