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Akbar G Ali

from Coto de Caza, CA
Age ~75

Akbar Ali Phones & Addresses

  • Coto de Caza, CA
  • Irvine, CA
  • Vallejo, CA
  • Torrance, CA
  • Mission Viejo, CA

Professional Records

License Records

Akbar Ali

License #:
12854 - Expired
Issued Date:
Jan 30, 1991
Renew Date:
May 31, 2000
Expiration Date:
May 31, 2000
Type:
Certified Public Accountant

Akbar Nadeem Ali

License #:
278571
Category:
Physician
Issued Date:
Feb 20, 2015
Type:
MEDICINE

Akbar Nasera Ali

License #:
039251
Category:
Pharmacist
Issued Date:
Apr 12, 1989
Type:
PHARMACY

Medicine Doctors

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Akbar Ali

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Specialties:
General Surgery
Work:
Zia Medical Specialists
601 W Country Clb Rd STE 201, Roswell, NM 88201
(575) 627-0535 (phone), (575) 627-5590 (fax)
Education:
Medical School
Sind Med Coll, Univ of Karachi, Karachi, Pakistan
Graduated: 1987
Procedures:
Appendectomy
Breast Biopsy
Breast Reduction
Colonoscopy
Gallbladder Removal
Hemorrhoid Procedures
Hernia Repair
Laparoscopic Appendectomy
Laparoscopic Gallbladder Removal
Mastectomy
Pilonidal Cyst Excision
Skin Tags Removal
Small Bowel Resection
Upper Gastrointestinal Endoscopy
Conditions:
Abdominal Hernia
Appendicitis
Benign Neoplasm of Breast
Breast Disorders
Cholelethiasis or Cholecystitis
Languages:
English
Spanish
Description:
Dr. Ali graduated from the Sind Med Coll, Univ of Karachi, Karachi, Pakistan in 1987. He works in Roswell, NM and specializes in General Surgery. Dr. Ali is affiliated with Eastern New Mexico Medical Center.

Resumes

Resumes

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Akbar Ali

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Skills:
Speaks: Englies, Tamil, Hindi, Arabic, Malayalam
Akbar Ali Photo 3

Akbar Ali US

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Work:
Advantage Finvest corporation ltd

Team Leader

Icici bank ltd

Sep 2007 to Jun 2010
Team leader

Education:
Bundelkhand University
2007
B.A.

Govt. Inter College
2004

Guru Nanak Khalsa Inter College
2001

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Akbar Ali US

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Work:
Pakistan Atomic Energy Commision& General

Jun 2012 to Aug 2012
Consultant Anesthesiologist

Holy Family Hospital

Mar 2009 to Jun 2012
Assistant Anesthetist

Holy Family Hospital

Mar 2009 to Dec 2011
Post graduate Resident anesthesiology

P.I.M.S, Islamabad, Pakistan

Jan 2008 to Mar 2009
Post graduate Resident anesthesiology

BHU

May 2006 to May 2007
Medical Officer

House job General Surgery

Jan 2005 to May 2006
Consultant anesthesiologist

House job General

Jan 2005 to Nov 2005

Business Records

Name / Title
Company / Classification
Phones & Addresses
Akbar Ali
DAR-E-ZEHRA

Publications

Us Patents

Programmable Relaxation Oscillator

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US Patent:
6377129, Apr 23, 2002
Filed:
Apr 30, 1999
Appl. No.:
09/302754
Inventors:
Woogeun Rhee - Irvine CA
Akbar Ali - Garden Grove CA
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
H03K 3282
US Classification:
331111, 331143, 331144, 331113 R, 331 36 C, 331 34
Abstract:
An oscillator has a slope-fixing circuit that generates a control signal and fixes the slope of the control signal, a swing-fixing circuit that fixes the swing of the control signal, and a switching block that generates an output signal having a frequency derived from the swing and the slope of the control signal. The slope-fixing circuit comprises a fixed timing capacitor C in parallel with a plurality of switchable timing capacitors C. . . C to provide an effective capacitance C. The slope of the control signal is determined by the ratio of a control current I to the effective capacitance C. The swing-fixing circuit comprises a replica cell that accepts a programmable reference voltage V and provides a fixed voltage swing V =V -V across a pair of load transistors. The switching block comprises a pair of switching transistors that alternate between “on” and “off” states depending on the value of the control signal to produce an oscillating output signal. The frequency of the output signal is given by.

Effectively Differential, Multiple Input Or/Nor Gate Architecture

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US Patent:
5945848, Aug 31, 1999
Filed:
Nov 19, 1996
Appl. No.:
8/752016
Inventors:
Akbar Ali - Garden Grove CA
Assignee:
Rockwell Semiconductor Systems, Inc. - Newport Beach CA
International Classification:
H03K 19086
US Classification:
326127
Abstract:
A multiple input, low voltage, OR/NOR gate architecture based on a single-ended OR/NOR gate circuit, wherein a plurality of input transistors are connected in parallel. A reference transistor connects to the input transistors. A feedback means connects the NOR output signal to the base or gate of the reference transistor. The feedback means provides an effectively differential input for the multiple input circuit, without increasing circuit complexity, thereby providing enhanced noise margin characteristics.

Interlaced Master-Slave Ecl D Flip-Flop

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US Patent:
6191629, Feb 20, 2001
Filed:
Sep 27, 1999
Appl. No.:
9/405964
Inventors:
Biagio Bisanti - Antibes,
Akbar Ali - Garden Grove CA
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
H03K 3289
US Classification:
327202
Abstract:
A D flip-flop circuit operating in master-slave configuration which has low power consumption and is capable of high-speed operation, and a method for lowering power consumption in such a circuit is provided. The circuit embodiment includes two latches, each with a switching and memory section, and two interlaced current sources. In response to the active high clock signal the master latch memory section uses the current from the first current source while the slave latch switching section uses the current from the second current source, and vice versa. The switching section of each latch is biased with a higher current than the memory section, to provide the circuit with low power consumption. The output current provided to the switching section is preferably substantially twice the magnitude of the current provided to the memory section. The ratio of the currents of the current sources for the switching and memory section is preferably in the range of about 30% to 70%, depending on the clock frequency.

Phase/Frequency Detector With Time-Delayed Inputs In A Charge Pump Based Phase Locked Loop And A Method For Enhancing The Phase Locked Loop Gain

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US Patent:
6147561, Nov 14, 2000
Filed:
Jul 29, 1999
Appl. No.:
9/363779
Inventors:
Woogeun Rhee - Irvine CA
Akbar Ali - Garden Grove CA
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
H03L 700
US Classification:
331 12
Abstract:
A phase locked loop (PLL) circuit with time-delayed phase/frequency detector (PFD) input signals and a method for generating high PFD gain in such a circuit is provided. One circuit embodiment includes a first divider, a phase/frequency detector having a plurality of input pairs, a plurality of input signal reference delay elements connected in a series between the first divider and the PFD, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), a second divider, and a plurality of feedback signal delay elements connected in a series. The corresponding method embodiment includes steps for receiving digital input signals with reference frequency and period T in the first divider, dividing the reference frequency by a value R, providing a plurality of time-delayed PFD reference input signals in each period T, dividing the VCO frequency by a value M in the second divider, and providing a plurality of time-delayed PFD feedback input signals in each period T. The delayed reference signal and the delayed feedback signal at each PFD input pair have the same time delay. Another embodiment circuit has a first divider, a plurality of phase/frequency detectors (PFDs), a charge pump, two OR gates, a loop filter, a voltage-controlled oscillator (VCO), and a second divider.

Differential Lc-Vco, Charge Pump, And Loop Filter Architecture For Improved Noise-Immunity In Integrated Phase-Locked Loops

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US Patent:
6281758, Aug 28, 2001
Filed:
Sep 30, 1999
Appl. No.:
9/409509
Inventors:
Ayman M. Elsayed - Waterloo,
Akbar Ali - Garden Grove CA
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
H03B 512
H03L 7093
H03L 7099
US Classification:
331 16
Abstract:
A differential LC-based voltage-controlled oscillator (LC-VCO), charge pump and loop filter architecture for providing improved noise immunity in integrated phase-locked loops (PLLs). A pair of voltage control signals are provided from a differential charge pump and loop filter architecture to respective voltage control inputs in the LC-VCO to differentially control the LC-VCO. The voltage control inputs are connected to respective terminals on opposite ends of a varactor tuning circuit. The differential voltage applied across the varactor tuning circuit determines the LC characteristics of the varactor tuning circuit which, in turn, determines the operating frequency of the VCO. One of the voltage control inputs is passed through an operational amplifier buffering stage before being transmitted to its respective terminal in the varactor tuning circuit. The LC-VCO utilizes a PMOS transistor core to provide good substrate isolation and low flicker (1/f) noise. The PMOS core further eliminates parasitic diode problems while maintaining the whole supply range for tuning.

Phase-Locked Loop Having Temperature-Compensated Bandwidth Control

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US Patent:
6211743, Apr 3, 2001
Filed:
May 19, 1999
Appl. No.:
9/314898
Inventors:
Woogeun Rhee - Irvine CA
Akbar Ali - Garden Grove CA
Matteo Conta - Irvine CA
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
H03L 102
H03L 708
US Classification:
331 34
Abstract:
A phase-locked loop includes a phase/frequency detector, a charge pump, a loop filter, an oscillator and a feedback circuit coupled between the oscillator and the phase/frequency detector. The loop filter includes a first temperature-variable well resistor and has a gain directly related to resistance of the first resistor. An oscillator coupled to the loop filter includes a voltage-to-current converter that generates a reference current based on the loop filter voltage, and a current-controlled oscillator that generates the output clock based on the value of the reference current. The voltage-to-current converter includes a first transistor that receives the loop filter voltage at a gate and a second temperature-variable well resistor coupled to the source of the first transistor. The oscillator gain is indirectly related to the resistance of the second resistor. The second well resistor and first well resistor have substantially equal resistances and substantially equal temperature coefficients.

Fully Integrated Broadband Rf Voltage Amplifier With Enhanced Voltage Gain And Method

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US Patent:
6265944, Jul 24, 2001
Filed:
Sep 27, 1999
Appl. No.:
9/405766
Inventors:
Matteo Conta - Irvine CA
Akbar Ali - Garden Grove CA
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
H03F 345
H03F 304
H03F 314
US Classification:
330302
Abstract:
RF voltage amplifier circuits which have high voltage amplifier gain and input signal frequency range, and a method for boosting the voltage amplifier gain and input signal frequency range in such circuits is provided. A method includes the steps of providing a voltage amplifier having a transistor with the grounded source and the drain connected to a power supply via a resistive load, and providing an integrated inductor for biasing the transistor, having an inductor connecting an input signal terminal to the gate of the transistor and a capacitor connecting the gate and the source of the transistor. The next step includes selecting a resonant frequency of the integrated inductor at a frequency where the voltage amplifier gain is starting to roll-off, for boosting the voltage amplifier gain and the input signal frequency range. The integrated inductor preferably operates at a resonant frequency approximately matching the roll-off frequency of the voltage amplifier. In another embodiment the voltage amplifier has a common emitter (CE) gain stage, a common base (CB) cascade stage directly-coupled to the CE gain stage, and a constant current mirror source.

Cmos Electrostatic Discharge Protection Circuit With Minimal Loading For High Speed Circuit Applications

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US Patent:
6292046, Sep 18, 2001
Filed:
Sep 30, 1998
Appl. No.:
9/163675
Inventors:
Akbar Ali - Garden Grove CA
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
H03K 508
US Classification:
327310
Abstract:
The present invention relates to a circuit for protecting inputs and outputs on semiconductor devices. The protective circuit is particularly useful on high-speed inputs or outputs (such as in radio frequency applications where signal frequency is on the order of 100 MHz or greater and where it is necessary to minimize capacitive loading. Briefly, the present invention utilizes two FETs to shunt harmful electrostatic charges to a low impedance power bus and protect input and output circuit elements from damage or degradation. When a high voltage transient surge is detected, the drain-gate capacitance of one of the FETs couples the voltage to the gate electrode and biases one of the two transistors in the low impedance state so that the surge is absorbed without damage to the input or output circuit. Significantly, the capacitive loading of the protection circuit of the present invention is typically a fraction of a picoFarad and more particularly on the order of several hundred femtofarads.

Wikipedia References

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Akbar Ali

About:
Born:

1925

Education:
Academic degree:

Professor • MA

Akbar G Ali from Coto de Caza, CA, age ~75 Get Report