Resumes
Resumes
Technical Lead
View pageLocation:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Semiconductors
Work:
Intel since Feb 2002
Engineering Manager
Engineering Manager
Education:
Arizona State University 1996 - 1997
Skills:
Extensive Experience In Complex Mixed Signal Circuit Design
Dft
Integration
Technical Leadership
Verilog
Business
Static Timing Analysis
Mixed Signal
Pll
Social Media
Cadence
Low Power Design
Cmos
Soc
Circuit Design
Social Networking
Asic
Analog
Vlsi
Analog Circuit Design
Simulations
System on A Chip
Very Large Scale Integration
Phase Locked Loop
Application Specific Integrated Circuits
Dft
Integration
Technical Leadership
Verilog
Business
Static Timing Analysis
Mixed Signal
Pll
Social Media
Cadence
Low Power Design
Cmos
Soc
Circuit Design
Social Networking
Asic
Analog
Vlsi
Analog Circuit Design
Simulations
System on A Chip
Very Large Scale Integration
Phase Locked Loop
Application Specific Integrated Circuits
Languages:
Bengali