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Adithya Yalavarti

from Acton, MA
Age ~53
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Also known as:
Yalavarti Adithya, A Yalavarti
Phone and address:
4 Beth Cir, Acton, MA 01720
Connected to:
Nitesh Yalavarthi, 33Alan Yalch, 60Janet R Yalch, 67Cemal Yalcin, 42Cuneyt Yalcin, 46Erdem Yalcin, 61Muge Yalcin, 37Tarik S Yalcin, 37Tolga Yalcin, 53Zeynep Yalcin, 37

Adithya Yalavarti Phones & Addresses

  • 4 Beth Cir, Acton, MA 01720
  • Urbana, IL
  • 1010 Clark St, Champaign, IL 61821 (217) 344-7486

Work

Company: Amd Jul 2013 to Jun 2015 Position: Member of technical staff design engineer

Education

Degree: Master of Science, Masters School / High School: University of Illinois at Urbana - Champaign 2004 to 2006 Specialities: Computer Engineering

Skills

Computer Architecture • C++ • Verilog • Microprocessors • Vlsi • C • Systemverilog • Debugging • Algorithms • Functional Verification • Processors • Java • Perl • Rtl Design • Microarchitecture • Vhdl • Post Silicon Debug • X86 Assembly • Stimulus Generation • Very Large Scale Integration • Hardware Emulation • Formal Verification

Languages

English • Telugu • Hindi

Industries

Semiconductors

Resumes

Resumes

Adithya Yalavarti Photo 1

Principal Member Of Technical Staff

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Location:
4 Beth Cir, Acton, MA 01720
Industry:
Semiconductors
Work:
Amd Jul 2013 - Jun 2015
Member of Technical Staff Design Engineer
Vision Biotech 2008 - 2014
Co-Founder
Amd Oct 2009 - Jun 2013
Senior Design Engineer
Amd Jun 2006 - Sep 2009
Senior Member of Technical Staff Design Engineer
Amd Jun 2006 - Sep 2009
Principal Member of Technical Staff
Education:
University of Illinois at Urbana - Champaign 2004 - 2006
Master of Science, Masters, Computer Engineering
Skills:
Computer Architecture
C++
Verilog
Microprocessors
Vlsi
C
Systemverilog
Debugging
Algorithms
Functional Verification
Processors
Java
Perl
Rtl Design
Microarchitecture
Vhdl
Post Silicon Debug
X86 Assembly
Stimulus Generation
Very Large Scale Integration
Hardware Emulation
Formal Verification
Languages:
English
Telugu
Hindi

Publications

Us Patents

Increase Cache Associativity Using Hot Set Detection

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US Patent:
20180052778, Feb 22, 2018
Filed:
Aug 22, 2016
Appl. No.:
15/243921
Inventors:
- Sunnyvale CA, US
Adithya Yalavarti - Boxborough MA, US
Johnsy Kanjirapallil John - Acton MA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 12/12
G06F 12/0864
G06F 12/0893
G06F 12/0891
Abstract:
A processing apparatus and a method of accessing data using cache hot set detection is provided that includes receiving a plurality of requests to access data in a cache. The cache includes a plurality of cache sets each including N number of cache lines. Each request includes an address. The apparatus and a method also includes storing, in a HSVC array, cache line victims of one or more of the plurality of cache sets determined to be hot sets. Each cache line victim includes a corresponding address that is determined, using a HSD array, to belong to the one or more determined cache hot sets based on a hot set frequency of a plurality of addresses mapped to the set in the cache.
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Adithya Yalavarti from Acton, MA, age ~53 Get Report