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Adi R Ofer

from San Jose, CA
Age ~57

Adi Ofer Phones & Addresses

  • 3266 Pearltone Dr, San Jose, CA 95117
  • 970 Asilomar Ter #5, Sunnyvale, CA 94086 (781) 237-3470
  • 550 Moreland Way #4207, Santa Clara, CA 95054
  • 10 Merriam Rd, Framingham, MA 01701 (508) 788-0202 (508) 237-3470
  • 96 Washburn Ave, Wellesley Hills, MA 02481 (781) 237-3470
  • Wellesley, MA
  • Somerville, MA
  • Cambridge, MA
  • 970 Asilomar Ter APT 5, Sunnyvale, CA 94086

Work

Company: Netskope Dec 2017 Position: Vice president engineering

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Harvard University 1993 to 1997 Specialities: Mathematics

Skills

Storage • Distributed Systems • Software Engineering • System Architecture • Software Development • Cloud Computing • Big Data • Scalability • Linux • Algorithms • Technical Leadership • C++ • Perl • Virtualization

Industries

Computer Software

Resumes

Resumes

Adi Ofer Photo 1

Vice President Engineering

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Location:
1938 north 73Rd Ct, Elmwood Park, IL 60707
Industry:
Computer Software
Work:
Netskope
Vice President Engineering

Uber Sep 2016 - Nov 2017
Director of Engineering, Data Infrastructure, Storage, and Autonomous Vehicle Infrastructure

Rubrik, Inc. Sep 2015 - Sep 2016
Senior Director of Engineering

The Great Wide World Aug 2013 - Aug 2015
Globe Trotter

Google Aug 2011 - Sep 2012
Engineering Director, Google+ Back-End
Education:
Harvard University 1993 - 1997
Doctorates, Doctor of Philosophy, Mathematics
Harvard University 1993 - 1995
Masters, Master of Arts, Mathematics
Massachusetts Institute of Technology 1992 - 1993
Doctorates, Doctor of Philosophy, Computer Science
The Hebrew University of Jerusalem 1989 - 1992
Bachelors, Bachelor of Arts, Mathematics, Computer Science
Skills:
Storage
Distributed Systems
Software Engineering
System Architecture
Software Development
Cloud Computing
Big Data
Scalability
Linux
Algorithms
Technical Leadership
C++
Perl
Virtualization

Publications

Us Patents

Cache Using Multiple Lrus

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US Patent:
6457102, Sep 24, 2002
Filed:
Nov 5, 1999
Appl. No.:
09/434611
Inventors:
Daniel Lambright - Waltham MA
Adi Ofer - Wellesley MA
Natan Vishlitzky - Brookline MA
Yuval Ofek - Framingham MA
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 1208
US Classification:
711129, 711131, 711152
Abstract:
Storing data in a cache memory includes providing a first mechanism for allowing exclusive access to a first portion of the cache memory and providing a second mechanism for allowing exclusive access to a second portion of the cache memory, where exclusive access to the first portion is independent of exclusive access to the second portion. The first and second mechanisms may be software locks. Allowing exclusive access may also include providing a first data structure in the first portion of the cache memory and providing a second data structure in the second portion of the cache memory, where accessing the first portion includes accessing the first data structure and accessing the second portion includes accessing the second data structure. The data structures may doubly linked ring lists of blocks of data and the blocks may correspond to a track on a disk drive. The technique described herein may be generalized to any number of portions.

Selective Validation For Queued Multimodal Locking Services

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US Patent:
6609178, Aug 19, 2003
Filed:
Nov 28, 2000
Appl. No.:
09/723606
Inventors:
Adi Ofer - Wellesley MA
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 1214
US Classification:
711152, 711163, 710200
Abstract:
A queued, multimodal, self-validating lock mechanism selectively associates supplemental validation procedures with certain lock modes. Only those lock modes which heavily drain system resources are extensively validated.

Logical Volume Selection In A Probability-Based Job Scheduler

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US Patent:
6665740, Dec 16, 2003
Filed:
Nov 12, 1999
Appl. No.:
09/439903
Inventors:
Adi Ofer - Wellesley MA
Natan Vishlitzky - Brookline MA
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 300
US Classification:
710 6, 710 5, 710 7, 711112, 711114
Abstract:
A scheduler for selecting a logical volume for job generation based on the loading of physical resources in a data storage system. The scheduler determines a job workload for each of the physical resources, selects physical resources based on the job workload and selects a logical volume supported by the selected physical resources in a balanced manner.

Selective Association Of Lock Override Procedures With Queued Multimodal Lock

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US Patent:
6691194, Feb 10, 2004
Filed:
Nov 28, 2000
Appl. No.:
09/724044
Inventors:
Adi Ofer - Wellesley MA
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 1200
US Classification:
710200, 710240, 711151, 711152
Abstract:
A queued, multimodal, fault-tolerant lock mechanism for managing shared resources in a data processing system is provided. Lock override procedures are selectively associated with certain lock modes.

Hierarchical Approach To Indentifying Changing Device Characteristics

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US Patent:
6701392, Mar 2, 2004
Filed:
Nov 30, 2001
Appl. No.:
09/998494
Inventors:
Mark J. Halstead - Waltham MA
Adi Ofer - Wellesley MA
Dan Arnon - Boston MA
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 300
US Classification:
710 36, 710 5, 710 16, 710 37, 710 38, 711122
Abstract:
Determining device characteristics includes obtaining a first globally accessible value, if the first globally accessible value corresponds to a stored first value, obtaining device characteristics data from a relatively fast memory, if the first globally accessible value does not correspond to the stored first value, obtaining a second globally accessible value, if the second globally accessible value corresponds to a stored second value, obtaining device characteristics data from a relatively fast memory, if the second globally accessible value does not correspond to the stored second value, obtaining device characteristics data from a relatively slow memory and updating the relatively fast memory, the stored first value, and the stored second value. The globally accessible first value may include device I/O information. The globally accessible values may be stored in global memory that is accessible to a plurality of processors.

Queued Locking Of A Shared Resource Using Multimodal Lock Types

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US Patent:
6718448, Apr 6, 2004
Filed:
Nov 28, 2000
Appl. No.:
09/724043
Inventors:
Adi Ofer - Wellesley MA
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 1214
US Classification:
711163, 711147, 711152, 711155, 707 8, 710200
Abstract:
A lock for managing shared resources in a data processing system enables a requesting processor, in a signal atomic transaction, to validate the main lock data structure, request a lock, take the lock and establish a lock mode if successful, or establish its place in a queue of requesters for subsequent locks on the shared resource if unsuccessful.

Segmenting Cache To Provide Varying Service Levels

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US Patent:
6728836, Apr 27, 2004
Filed:
Mar 24, 2000
Appl. No.:
09/535134
Inventors:
Daniel Lambright - Watertown MA
Adi Ofer - Wellesley MA
Natan Vishlitzky - Brookline MA
Yuval Ofek - Framingham MA
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 1208
US Classification:
711129
Abstract:
Storing data in a cache memory of a storage device includes providing access to a first segment of the cache memory on behalf of a first group of external host systems coupled to the storage device and providing access to a second segment of the cache memory on behalf of a second group of external host systems coupled to the storage device, where at least a portion of the second segment of the cache memory is not part of the first segment of the cache memory. In some embodiments, no portion of the second segment of the cache memory is part of the first segment. Storing data in a cache memory of a storage device may also include providing a first data structure in the first segment of the cache memory and providing a second data structure in the second segment of the cache memory, where accessing the first segment includes accessing the first data structure and accessing the second segment includes accessing the second data structure. The data structures may be doubly linked ring lists of blocks of data. Each block of data may correspond to a track on a disk drive.

Method And Apparatus For Multi-Sequential Data Operations

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US Patent:
6732194, May 4, 2004
Filed:
Jun 27, 2001
Appl. No.:
09/893295
Inventors:
Haim Kopylovitz - Brookline MA
Adi Ofer - Wellesley MA
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 300
US Classification:
710 5, 710 7, 710 36, 711113, 711148
Abstract:
Described are techniques for performing multi-sequential I/O operations in connection with data requests involving a data storage device. An single data request may involve more than a one portion of data associated with a single job record, such as a single request may involve more than a single track of data of a logical device. A single job record corresponds to a single track. A data structure arrangement is disclosed that includes multiple job records corresponding to the single data request involving more than a single track of data. The multiple job records for a single data request are connected together in a data structure arrangement that may be used in connection with a single read operation involving more than a single track of data. This data structure may also be used in connection with storing a plurality of pending write requests, such as in connection with writing data from cache locations to a plurality of tracks of a particular device in which the plurality of pending write requests are represented as a single data request.
Adi R Ofer from San Jose, CA, age ~57 Get Report