Search

Adel A Elsherbini

from Chandler, AZ
Age ~41
Get Report
Connected to:
Kitty Elsherif, 43Nahla Elsherif, 40Suzanne Elsherif, 34Ahmed N Elsheshaiy, 36Hatim B Elshiekh, 46Brenda B Elshof, 70Phyllis L Elshof, 87Tate B Elshof, 32Daniel J Elshoff, 56Kristina M Elshoff, 37

Adel Elsherbini Phones & Addresses

  • Chandler, AZ
  • Tempe, AZ
  • Ann Arbor, MI

Resumes

Resumes

Adel Elsherbini Photo 1

Principal Engineer

View page
Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Telecommunications
Work:
Intel Corporation - Chandler, AZ since Jun 2011
Research Scientist
Ain Shams University since Feb 2005
Teaching and Research Assistant
University of Michigan Sep 2007 - May 2011
Graduate Student Research Assistant
Intel May 2010 - Aug 2010
Summer Intern
Education:
University of Michigan 2007 - 2011
PhD, Electrical Engineering University of Tennessee-Knoxville 2006 - 2006
Visiting Scholar, Antennas and Microwave Engineering Otto-von-Guericke-Universität Magdeburg 2005 - 2005
Visiting Scholar, Electromagnetics Ain Shams University 2004 - 2004
M.Sc., Electrical Engineering
Skills:
Matlab
Simulations
Antennas
Radar
Synthetic Aperture Radar
Circuit Design
Microwave
Agilent Ads
Analog Circuit Design
Electromagnetics
Rf
Signal Processing
Ic
Electrical Engineering
Analog
Algorithms
Semiconductors
Interests:
Table Tennis
Reading
Science and Technology
Tennis
Swimming
Languages:
English
Arabic
Adel Elsherbini Photo 2

Principal Engineer

View page
Location:
Chandler, AZ
Work:
Intel Corporation
Principal Engineer

Publications

Us Patents

Inductor And Transformer Semiconductor Devices Using Hybrid Bonding Technology

View page
US Patent:
20220415555, Dec 29, 2022
Filed:
Jun 25, 2021
Appl. No.:
17/359165
Inventors:
- Santa Clara CA, US
Qiang Yu - Saratoga CA, US
Adel Elsherbini - Tempe AZ, US
Kimin Jun - Portland OR, US
International Classification:
H01F 27/06
H01L 23/64
H01L 23/522
H01L 23/528
H01L 49/02
H01F 27/28
H01L 21/50
Abstract:
Methods and apparatus for inductor and transformer semiconductor devices using hybrid bonding technology are disclosed. An example semiconductor device includes a first standoff substrate; a second standoff substrate adjacent the first standoff substrate; and a conductive layer adjacent at least one of the first standoff substrate or the second standoff substrate.

Thermal Performance In Hybrid Bonded 3D Die Stacks

View page
US Patent:
20220415743, Dec 29, 2022
Filed:
Jun 25, 2021
Appl. No.:
17/358361
Inventors:
- Santa Clara CA, US
Adel Elsherbini - Tempe AZ, US
Johanna Swan - Scottsdale AZ, US
Shawna Liff - Scottsdale AZ, US
Aleksandar Aleksov - Chandler AZ, US
Julien Sebot - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/36
H01L 25/065
H01L 21/50
H01L 27/06
H01L 23/00
Abstract:
Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

Device, Method And System To Mitigate Stress On Hybrid Bonds In A Multi-Tier Arrangement Of Chiplets

View page
US Patent:
20220415837, Dec 29, 2022
Filed:
Jun 25, 2021
Appl. No.:
17/359380
Inventors:
- Santa Clara CA, US
Feras Eid - Chandler AZ, US
Adel Elsherbini - Tempe AZ, US
Aleksandar Aleksov - Chandler AZ, US
Shawna Liff - Scottsdale AZ, US
Johanna Swan - Scottsdale AZ, US
Julien Sebot - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/00
H01L 25/065
H01L 23/31
H01L 21/56
H01L 25/00
Abstract:
Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.

Universal Hybrid Bonding Surface Layer Using An Adaptable Interconnect Layer For Interface Disaggregation

View page
US Patent:
20220415839, Dec 29, 2022
Filed:
Jun 24, 2021
Appl. No.:
17/357722
Inventors:
- Santa Clara CA, US
Feras EID - Chandler AZ, US
Johanna M. SWAN - Scottsdale AZ, US
Adel A. ELSHERBINI - Chandler AZ, US
Shawna M. LIFF - Scottsdale AZ, US
International Classification:
H01L 23/00
H01L 25/065
Abstract:
Embodiments disclosed herein include semiconductor dies with hybrid bonding layers and multi-die modules that are coupled together by hybrid bonding layers. In an embodiment, a semiconductor die comprises a die substrate, a pad layer over the die substrate, where the pad layer comprises first pads with a first dimension and a first pitch and second pads with a second dimension and a second pitch. In an embodiment, the semiconductor die further comprises a hybrid bonding layer over the pad layer. In an embodiment, the hybrid bonding layer comprises a dielectric layer, and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads comprise a third dimension and a third pitch.

Features For Improving Die Size And Orientation Differentiation In Hybrid Bonding Self Assembly

View page
US Patent:
20220415847, Dec 29, 2022
Filed:
Jun 24, 2021
Appl. No.:
17/357729
Inventors:
- Santa Clara CA, US
Johanna M. SWAN - Scottsdale AZ, US
Shawna M. LIFF - Scottsdale AZ, US
Adel A. ELSHERBINI - Chandler AZ, US
Aleksandar ALEKSOV - Chandler AZ, US
International Classification:
H01L 23/00
H01L 25/065
H01L 23/498
Abstract:
Embodiments disclosed herein include multi-die modules and methods of assembling multi-die modules. In an embodiment, a multi-die module comprises a first die. In an embodiment the first die comprises a first pedestal, a plateau around the first pedestal, and a stub extending up from the plateau. In an embodiment, the multi-die module further comprises a second die. In an embodiment, the second die comprises a second pedestal, where the second pedestal is attached to the first pedestal.

Heat Insulating Interconnect Features In A Component Of A Composite Ic Device Structure

View page
US Patent:
20220415853, Dec 29, 2022
Filed:
Jun 25, 2021
Appl. No.:
17/358948
Inventors:
- Santa Clara CA, US
Johanna Swan - Scottsdale AZ, US
Shawna Liff - Scottsdale AZ, US
Feras Eid - Chandler AZ, US
Adel Elsherbini - Tempe AZ, US
Julien Sebot - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 25/065
H01L 25/18
H01L 23/00
H01L 25/00
Abstract:
A composite integrated circuit (IC) structure includes at least a first IC die in a stack with a second IC die. Each die has a device layer and metallization layers interconnected to transistors of the device layer and terminating at features. First features of the first IC die are primarily of a first composition with a first microstructure. Second features of the second IC die are primarily of a second composition or a second microstructure. A first one of the second features is in direct contact with one of the first features. The second composition has a thermal conductivity at least an order of magnitude lower than that of the first composition and first microstructure. The first composition may have a thermal conductivity at least 40 times that of the second composition or second microstructure.

Apparatus And Method To Integrate Three-Dimensional Passive Components Between Dies

View page
US Patent:
20220415854, Dec 29, 2022
Filed:
Jun 25, 2021
Appl. No.:
17/359481
Inventors:
Adel Elsherbini - Tempe AZ, US
Qiang Yu - Saratoga CA, US
Shawna Liff - Scottsdale AZ, US
Beomseok Choi - Chandler AZ, US
International Classification:
H01L 25/065
H01L 27/06
H01L 49/02
H01L 23/66
Abstract:
Apparatus and methods are disclosed. In one example, a semiconductor package includes a first die that has a first surface and a first electrical lead at or near the first surface. The semiconductor package also includes a substrate that has a second surface and is coupled to the first die at a first interface. The substrate also includes a first electrode at or near the second surface and at least a first portion of an integrated passive device that is coupled to the first electrode. The first electrode is aligned with and coupled to the first electrical lead across the first interface.

Waveguide Interconnects For Semiconductor Packages And Related Methods

View page
US Patent:
20220416393, Dec 29, 2022
Filed:
Jun 25, 2021
Appl. No.:
17/359138
Inventors:
- Santa Clara CA, US
Johanna Swan - Scottsdale AZ, US
Adel Elsherbini - Tempe AZ, US
Shawna Liff - Scottsdale AZ, US
Beomseok Choi - Chandler AZ, US
Qiang Yu - Saratoga CA, US
International Classification:
H01P 3/16
H01L 25/065
H01P 1/208
H01L 23/538
H01P 5/107
H01L 23/66
Abstract:
Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.
Control profile
Adel A Elsherbini from Chandler, AZ, age ~41 Get Report