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Adam D Blot

from Altamont, NY
Age ~42
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Also known as:
Adam D Bolt, Adam Burt
Phone and address:
4 Frenchs Mill Rd, Altamont, NY 12009
(518) 339-7103
Related to:
Anna RitzQuerriero A TucciaroneChristopher Ritz, 30Tany CannistraciCarolynn Tucciarone, 75Jamie Blot, 38
Connected to:
Denis R Blot, 49Joseph Blot, 36Kim T Blot, 77Olivier C Blot, 58Tiffany Blot, 39Robert A Blotevogel, 61Shane D Blotkamp, 55David J Blotnick, 61Sheila M Blotnicki, 46Lindsay M Blotter, 35

Adam Blot Phones & Addresses

  • 4 Frenchs Mill Rd, Altamont, NY 12009 (518) 339-7103
  • Schenectady, NY
  • Troy, NY
  • East Greenbush, NY
  • Latham, NY
  • Albany, NY
  • 2017 William St, Schenectady, NY 12306

Work

Company: Benet laboratories May 2002 Position: Electrical engineer

Education

Degree: MS School / High School: Union College 2005 to 2010 Specialities: Engineering & Management Systems

Skills

Electrical Engineering • Matlab • Pcb Design • Engineering • Customer Service • Manufacturing • Circuit Design • Autocad • Systems Engineering • Project Management • Microcontrollers • Strategic Planning • Electronics • Embedded Systems • Hardware Architecture • Ptc Creo • Pro Engineer • Business Development • Leadership • Management • Microsoft Office • Product Development • Pads • Pro/Engineer • Hardware Design • Schematic Capture • Geometric Dimensioning and Tolerancing

Languages

English • Spanish

Ranks

Certificate: Asme Senior Level Certification: Geometric Dimensioning & Tolerancing Professional

Industries

Design

Public records

Vehicle Records

Adam Blot

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Address:
2017 William St, Schenectady, NY 12306
Phone:
(518) 339-7103
VIN:
2GKFLREK4C6152668
Make:
GMC
Model:
TERRAIN
Year:
2012

Resumes

Resumes

Adam Blot Photo 1

Lead Electrical Engineer At Transtech Systems, Inc

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Location:
Schenectady, NY
Industry:
Design
Work:
Benet Laboratories since May 2002
Electrical Engineer
Education:
Union College 2005 - 2010
MS, Engineering & Management Systems Rensselaer Polytechnic Institute 2003 - 2005
BS, Electrical Engineering
Skills:
Electrical Engineering
Matlab
Pcb Design
Engineering
Customer Service
Manufacturing
Circuit Design
Autocad
Systems Engineering
Project Management
Microcontrollers
Strategic Planning
Electronics
Embedded Systems
Hardware Architecture
Ptc Creo
Pro Engineer
Business Development
Leadership
Management
Microsoft Office
Product Development
Pads
Pro/Engineer
Hardware Design
Schematic Capture
Geometric Dimensioning and Tolerancing
Languages:
English
Spanish
Certifications:
Asme Senior Level Certification: Geometric Dimensioning & Tolerancing Professional
License Gdtp S-0617

Publications

Us Patents

Parallel Plate Capacitor System For Determining Impedance Characteristics Of Material Under Test (Mut)

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US Patent:
20210255161, Aug 19, 2021
Filed:
May 4, 2021
Appl. No.:
17/307114
Inventors:
- Latham NY, US
Adam D. Blot - Altamont NY, US
Andrew J. Westcott - Troy NY, US
International Classification:
G01N 33/24
G01R 31/50
A61B 5/0536
G01N 27/22
G01N 33/38
G01R 19/00
G01R 27/00
G01R 27/02
G01R 35/00
Abstract:
Various aspects of the disclosure relate to evaluating the electromagnetic impedance characteristics of a material under test (MUT) over a range of frequencies. In particular aspects, a system includes: an electrically non-conducting container sized to hold the MUT, the electrically non-conducting container having a first opening at a first end thereof and a second opening at a second, opposite end thereof; a transmitting electrode assembly at the first end of the electrically non-conducting container, the transmitting electrode assembly having a transmitting electrode with a transmitting surface; and a receiving electrode assembly at the second end of the electrically non-conducting container, the receiving electrode assembly having a receiving electrode with a receiving surface, wherein the receiving electrode is approximately parallel with the transmitting electrode, and wherein the transmitting surface of the transmitting electrode is larger than the receiving surface of the receiving electrode.

Parallel Plate Capacitor System For Determining Impedance Characteristics Of Material Under Test (Mut)

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US Patent:
20210055280, Feb 25, 2021
Filed:
Apr 23, 2019
Appl. No.:
16/640157
Inventors:
- Latham NY, US
Adam D. Blot - Altamont NY, US
Andrew J. Westcott - Troy NY, US
International Classification:
G01N 33/24
G01N 27/22
G01N 33/38
Abstract:
Various aspects of the disclosure relate to evaluating the electromagnetic impedance characteristics of a material under test (MUT) over a range of frequencies. In particular aspects, a system includes: an electrically non-conducting container sized to hold the MUT, the electrically non-conducting container having a first opening at a first end thereof and a second opening at a second, opposite end thereof; a transmitting electrode assembly at the first end of the electrically non-conducting container, the transmitting electrode assembly having a transmitting electrode with a transmitting surface; and a receiving electrode assembly at the second end of the electrically non-conducting container, the receiving electrode assembly having a receiving electrode with a receiving surface, wherein the receiving electrode is approximately parallel with the transmitting electrode, and wherein the transmitting surface of the transmitting electrode is larger than the receiving surface of the receiving electrode.

Electromagnetic Impedance Spectroscopy Apparatus And Related Planar Sensor System

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US Patent:
20200408708, Dec 31, 2020
Filed:
Jan 17, 2019
Appl. No.:
16/962621
Inventors:
- Latham NY, US
Adam D. Blot - Altamont NY, US
Andrew J. Westcott - Troy NY, US
International Classification:
G01N 27/02
G01N 27/22
Abstract:
According to various implementations, an apparatus for electromagnetic impedance spectra graphic characterization of a material under test (MUT) includes: a planar array of at least two electrodes configured to be placed in electromagnetic communication with the MUT, wherein during operation of the planar array, at least one of the electrodes comprises a transmitting electrode for transmitting an electromagnetic signal over a range of frequencies through the MUT to at least one receiving electrode in the planar array; and a backer ground plate at least partially surrounding the at least two electrodes, the backer ground plate being electrically grounded and insulated from the at least two electrodes, wherein the backer ground plate extends from a plane formed by the at least two electrodes and separates the at least two electrodes to create an electrically isolated volume proximate to the at least two electrodes.

System And Circuit For Obtaining Impedance Or Dielectric Measurements Of A Material Under Test

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US Patent:
20180172612, Jun 21, 2018
Filed:
Dec 14, 2017
Appl. No.:
15/841957
Inventors:
- Latham NY, US
Adam Blot - Altamont NY, US
International Classification:
G01N 27/02
Abstract:
Embodiments include a system and circuit for measuring characteristics of a material under test (MUT). In some cases, the system includes a circuit having level detectors to measure the change in strength between a reference signal and a return signal passed through the MUT. The system can include a computing device to evaluate the measured signals and adjust those signals within range of the level detectors and other circuit components. Circuits can include a time-of-flight digital convertor for determining the phase shift between the reference and return signals that pass through the MUT. The measured difference in signal strength and phase can be used to compute the complex impedance or dielectric properties of the MUT. This impedance or dielectric property can be correlated with a physical property of the MUT. The system may be operated at a single frequency, or over a range of frequencies.
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Adam D Blot from Altamont, NY, age ~42 Get Report