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Abhijit Radhakrishnan Phones & Addresses

  • 5124 Hibiscus Valley Dr, Austin, TX 78739
  • San Jose, CA
  • Santa Clara, CA
  • Los Angeles, CA

Work

Company: Apple Oct 2008 Position: Cpu implementation engineer (asic/layout engineer)

Education

School / High School: University of Southern California 2005 Specialities: MS in Electrical Engineering

Skills

Ip • Semiconductors • Cpu

Industries

Semiconductors

Resumes

Resumes

Abhijit Radhakrishnan Photo 1

Abhijit Radhakrishnan

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Location:
Austin, TX
Industry:
Semiconductors
Skills:
Ip
Semiconductors
Cpu
Abhijit Radhakrishnan Photo 2

Abhijit Radhakrishnan San Jose, CA

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Work:
Apple

Oct 2008 to 2000
CPU Implementation Engineer (ASIC/Layout Engineer)

Micron Technology
San Jose, CA
Apr 2008 to Oct 2008
Electrical Verification Engineer

Santa Clara

Aug 2005 to Apr 2008
Senior Implementation Engineer

Education:
University of Southern California
2005
MS in Electrical Engineering

Kerala University
2002
B.Tech in Electronics Engineering

Publications

Us Patents

Low Power And High Performance Physical Register Free List Implementation For Microprocessors

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US Patent:
20140013085, Jan 9, 2014
Filed:
Jul 3, 2012
Appl. No.:
13/541351
Inventors:
Suparn Vats - Fremont CA, US
John H. Mylius - Gilroy CA, US
Abhijit Radhakrishnan - Santa Clara CA, US
International Classification:
G06F 9/30
US Classification:
712217, 712E09016
Abstract:
A system and method for reducing latency and power of register renaming. A free list in processor includes multiple banks for indicating availability of register identifiers used for register renaming. A register rename unit receives one or more destination architectural registers to rename with physical register identifiers. Responsive to determining the multiple banks within the free list are unbalanced with available physical register identifiers, one or more returning physical register identifiers are assigned to the destination architectural registers before assigning any physical register identifiers from any bank of the multiple banks with a lowest number of available physical register identifiers. A returning physical register identifier is a physical register identifier that is available again for assignment to a destination architectural register but not yet indicated in the free list as available. Each of the banks includes a single bit width decoded vector for indicating availability of given physical register identifiers.
Abhijit Radhakrishnan from Austin, TX Get Report