Toan W Tran

6598132, Jul 22, 2003

Jul 18, 2001

09/908616

Toan D. Tran - Sunnyvale CA
Robert J. Divivier - San Jose CA
Siyad Ma - Palo Alto CA

Zettacom, Inc. - Santa Clara CA

G06F 1200

711154, 711122

A traffic manager for a network switch port includes a buffer memory and a buffer manager for writing incoming cells into the buffer memory and for thereafter reading the cells out of the buffer memory and forwarding them. The traffic manager also includes a queue manager for determining an order in which the buffer manager is to forward a set of cells stored in the buffer memory. The queue manager supplies the buffer manager with a sequence of pointers, each pointer referencing a separate cell of the set of cells, with the sequence of pointers being ordered to indicate an order in which the buffer manager is to forward the set of cells. After receiving the pointer sequence, the buffer manager changes the order of pointers in the pointer sequence to optimize a rate at which it can read the cells out of the buffer memory. The buffer manager reads the cells out of the buffer memory in an order indicated by the changed pointer sequence and thereafter forwards the cells read out of the buffer memory in the order in which the queue manager determined the cells are to be forwarded.

7058070, Jun 6, 2006

May 1, 2001

09/847079

Toan D. Tran - Sunnyvale CA, US
Robert J. Divivier - San Jose CA, US

Integrated Device Technology, Inc. - San Jose CA

H04L 12/28

370412, 370419, 370429

A network switch port includes a cell memory, a queuing system, a data path controller and an output buffer. The data path controller stores incoming cells derived from network data transmissions in the cell memory. The queuing system generates the cell memory address of each stored cell when the cell is to be forwarded from the cell memory, and the data path controller appends the cell memory address of that cell to a linked list of addresses of cells to be forwarded from the memory. When the linked list is not empty, the data path controller forwards cells from the cell memory to the output buffer in the order that their cell memory addresses were appended to the linked list. The output buffer stores and then sequentially forwards the cells outward from the switch port to a receiving network component which store them in a cell buffer until it can forward them elsewhere. The receiving network component produces a multiple bit back pressure data indicating how much of its cell buffer is currently filled with cells. Depending on the fill amount the back pressure data indicates, the output buffer either halts or continues to forward cells to the receiving network component, and either halts or continues allowing the data path controller to forward cells from the cell memory to the output buffer.

7204888, Apr 17, 2007

May 1, 2003

10/428967

Toan Q. Tran - San Jose CA, US
Daniel S. Herkalo - San Jose CA, US
Jin Ho Lee - Suwon Kyunggi, KR
Dong Hyung Lee - Suwon Kyunggi, KR
Jang Seok Oh - Suwon Kyunggi, KR
Won B. Bang - Santa Clara CA, US

Applied Materials, Inc. - Santa Clara CA

C23C 16/00
C23F 1/00
H01L 21/306

118728, 15634551, 15634552, 15634553, 15634554, 15634555, 118729, 118730

Embodiments of the present invention provide an apparatus for constraining and supporting the lift pins to prevent or minimize lateral movement of the lift pins that causes substrate hand-off problems and associated degradation in substrate processing characteristics and results. In one embodiment, a lift pin assembly for manipulating a substrate above a support surface of a substrate support comprises a plurality of lift pins movable between an up position and a down position. The lift pins include top ends and bottom ends. The top ends are configured to be lifted above the support surface of the substrate support to contact a bottom surface of the substrate in the up position. The top ends are configured to be positioned at or below the support surface of the substrate support in the down position. A lift pin connecting member is attached to the plurality of lift pins at attachment locations at or near the bottom ends of the lift pins to maintain fixed relative distances between the lift pins at the attachment locations and to move with the lift pins between the up position and the down position.

7806383, Oct 5, 2010

Jun 1, 2007

11/756632

Toan Q. Tran - San Jose CA, US
Lun Tsuei - Mountain View CA, US
Won Bang - Gilroy CA, US

Applied Materials, Inc. - Santa Clara CA

F16K 25/00

251193, 251175, 251328

Embodiments of a valve assembly for a process chamber having improved seal performance are provided herein. In some embodiments, a valve assembly for a process chamber includes a housing having an opening disposed in a wall thereof and through which a substrate may be transferred; a door movably coupled to the housing in a plane substantially parallel to the wall of the housing for selectively sealing the opening; a compressible sealing member disposed at least partly between an upper surface of the door and a corresponding surface of the housing for forming a seal therebetween by compression of the compressible sealing member in a direction substantially perpendicular to the wall when the door is in a closed position; and a mechanism for restricting the exposure of the compressible sealing member to an environment on a process chamber side of the housing.

7841582, Nov 30, 2010

Nov 16, 2004

10/990125

Won B. Bang - Santa Clara CA, US
Toan Q. Tran - San Jose CA, US

Applied Materials, Inc. - Santa Clara CA

F16K 25/00

251175, 251 3002, 251 94, 220240

Techniques for a door system for sealing an opening between two chambers in a semiconductor processing system are described. A sealing member seals the opening when a door is in a closed position. To selectively open and close the opening, an actuator moves the door. A valve actuator switch provides a first or second pressure to the actuator depending on the pressure inside a first chamber. In one embodiment, a sensor monitors the pressure inside the first chamber.

7872495, Jan 18, 2011

Jan 28, 2010

12/695992

Toan D. Tran - San Jose CA, US
Cheng H. Hsieh - Los Gatos CA, US
Mark J. Marlett - Livermore CA, US

Xilinx, Inc. - San Jose CA

H03K 19/003

326 30, 326 34

A unit cell for a programmable termination circuit in an integrated circuit and a method for programming such termination circuit are described. In an embodiment, such unit cells may have three n-type and three p-type transistors. A first transistor is coupled to receive a first float control signal. A second transistor is coupled to receive a second float control signal. The third and fourth transistors are coupled to receive a first termination voltage control signal. The fifth and sixth transistors are coupled to receive a second termination voltage control signal. The first float control signal and the second float control signal are a pair of complementary signals.

7989365, Aug 2, 2011

Aug 18, 2009

12/543245

Soonam Park - Mountain View CA, US
Soo Jeon - San Jose CA, US
Toan Q. Tran - San Jose CA, US
Qiwei Liang - Fremont CA, US
Dmitry Lubomirsky - Cupertino CA, US

Applied Materials, Inc. - Santa Clara CA

H01L 21/316

438788, 438792, 438905, 257E21278, 427574

Methods of seasoning a remote plasma system are described. The methods include the steps of flowing a silicon-containing precursor into a remote plasma region to deposit a silicon containing film on an interior surface of the remote plasma system. The methods reduce reactions with the seasoned walls during deposition processes, resulting in improved deposition rate, improved deposition uniformity and reduced defectivity during subsequent deposition.

8181140, May 15, 2012

Nov 9, 2009

12/615173

Vassili Kireev - Sunnyvale CA, US
James Karp - Saratoga CA, US
Toan D. Tran - San Jose CA, US

Xilinx, Inc. - San Jose CA

G06F 17/50

716122, 716123, 716129, 716130, 716132

A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon parasitic capacitance of a load coupled to an output of the T-coil network. An amount of electrostatic discharge (ESD) protection of the circuit design that is coupled to the output of the T-coil network and/or a parameter of the inductors of the T-coil network is selectively adjusted according to the comparison. The circuit design, which can specify inductance of the inductors, the amount of ESD protection, and/or the width of windings of the inductors, is outputted.