Syed S Alam

7358616, Apr 15, 2008

Sep 14, 2005

11/226025

Syed M. Alam - Austin TX, US
Robert E. Jones - Austin TX, US
Scott K. Pozder - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 23/48

257783, 257782, 257784, 257786, 257686, 257723, 257621, 257620, 257777, 257E25013, 257E23018

A reciprocal design symmetry allows stacked wafers or die on wafer to use identical designs or designs that vary only by a few layers (e. g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which may be used to decrease the interconnect required between the vertically stacked die and or wafers. Flipping and/or rotating may also be used to improve heat dissipation when wafer and/or die are stacked. The stacked wafers or die may then be packaged.

7715227, May 11, 2010

Oct 2, 2007

11/865991

Syed M. Alam - Austin TX, US
Robert E. Jones - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 11/50

365164, 365 51, 365 63

A read only memory implemented as a 3D integrated device has a first stratum, a second stratum, and bonded inter-strata connections for coupling the first stratum to the second stratum. The physical bonding between the two strata implements the programming of the read only memory. The stratum may be in wafer form or in die form. The first stratum includes functional active devices and at least one non-programmed active device. The second stratum includes at least conductive routing to be associated with the at least one non-programmed active device. The bonded inter-strata connections include at least one bonded programmable inter-strata connection for programming the at least one non-programmed active device and for providing conductive routing to the programmed active device. The two strata thus form a programmed ROM. Other types of programmable storage devices may be implemented by bonding the two strata.

20080113505, May 15, 2008

Nov 13, 2006

11/558988

Terry G. Sparks - Austin TX, US
Syed M. Alam - Austin TX, US
Ritwik Chatterjee - Austin TX, US
Shahid Rauf - Pleasanton CA, US

H01L 21/768

438637, 438667, 438687, 257E21577, 257E21586

A method for achieving a through-substrate via through a substrate having active circuitry on a first major surface begins by forming a hole into the substrate through the first major surface. The hole is lined with a conductive layer. A dielectric layer is deposited over the conductive layer. This deposition is performed in a manner that causes the dielectric layer to be substantially conformal. Conductive material is formed over first dielectric layer. A second major surface of the substrate is etched to expose the conductive material.

20120155160, Jun 21, 2012

Dec 16, 2011

13/328867

Syed M. Alam - Austin TX, US
Thomas Andre - Austin TX, US
Dietmar Gogl - Austin TX, US

EVERSPIN TECHNOLOGIES, INC. - Chandler AZ

G11C 7/00
G11C 11/02

365158, 3651892

A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).

20120195112, Aug 2, 2012

Jan 31, 2012

13/362599

Syed M. Alam - Austin TX, US
Thomas Andre - Austin TX, US
Matthew R. Croft - Austin TX, US
Chitra Subramanian - Mahopac NY, US
Halbert Lin - Austin TX, US

EVERSPIN TECHNOLOGIES, INC. - Chandler AZ

G11C 11/16

365158

A method includes destructively reading bits of a spin torque magnetic random access memory and immediately writing back the original or inverted values. A detection of the majority state of the write back bits and a conditional inversion of write back bits are employed to reduce the number of write back pulses. A subsequent write command received within a specified time or before an original write operation is commenced will cause a portion of the write back pulses or the original write operation pulses to abort. Write pulses during subsequent write operations will follow the conditional inversion determined for the write back bits during destructive read.

20120198313, Aug 2, 2012

Jan 31, 2012

13/362805

Syed M. Alam - Austin TX, US
Thomas Andre - Austin TX, US
Matthew R. Croft - Austin TX, US

EVERSPIN TECHNOLOGIES, INC. - Chandler AZ

H03M 13/05
G06F 11/10

714773, 714E11035

A method includes destructively reading bits of a spin torque magnetic random access memory, using error correcting code (ECC) for error correction, and storing inverted or non-inverted data in data-store latches. When a subsequent write operation changes the state of data-store latches, parity calculation and majority detection of the bits are initiated. A majority bit detection and potential inversion of write data minimizes the number of write current pulses. A subsequent write operation received within a specified time or before an original write operation is commenced will cause the majority detection operation to abort.

20120311396, Dec 6, 2012

May 31, 2012

13/484509

Thomas Andre - Austin TX, US
Syed M. Alam - Austin TX, US
Bradley Engel - Chandler AZ, US
Brian Butcher - Queen Creek AZ, US

EVERSPIN TECHNOLOGIES, INC. - Chandler AZ

H03M 13/05
G06F 11/10

714752, 714E11032

A method and memory device is provided for reading data from an ECC word of a plurality of reference bits associated with a plurality of memory device bits and determining if a double bit error in the ECC word exists. The ECC word may be first toggled twice and the reference bits reset upon detecting the double bit error.

20130272060, Oct 17, 2013

Mar 15, 2013

13/835426

Syed M. Alam - Austin TX, US
Chitra Subramanian - Mahopac NY, US

EVERSPIN TECHNOLOGIES, INC. - Chandler AZ

G11C 11/16

365158

Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column.