Professional Records
Medicine Doctors
Suresh Balasubramanian Phones & Addresses
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Folsom, CA
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Rocklin, CA
-
Sunnyvale, CA
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Fremont, CA
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2806 Treetrail Pkwy, Norcross, GA 30093 (678) 380-0907
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Duluth, GA
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1648 Quail Ave, Sunnyvale, CA 94087 (408) 234-9768
Work
Position:
Professional/Technical
Education
Degree:
Associate degree or higher
Resumes
Resumes
Head Of Solution Architecture At Tesco Plc
View pagePosition:
Head of Solution Architecture at Tesco PLC
Location:
Bengaluru, Karnataka, India
Industry:
Retail
Work:
Tesco PLC - Bengaluru Area, India since Feb 2013
Head of Solution Architecture
Head of Solution Architecture
Education:
Northwestern University - Kellogg School of Management 2006 - 2009
MBA, Strategy, Finance and Marketing College of Engineering, Guindy
Indian Institute of Technology, Delhi
MBA, Strategy, Finance and Marketing College of Engineering, Guindy
Indian Institute of Technology, Delhi
Skills:
Enterprise Architecture
E-commerce
Project Management
Software Development
IT Strategy
Strategic Planning
Strategy
Product Management
Leadership
ERP
Cross-functional Team Leadership
Project Planning
SDLC
Business Analysis
Integration
Vendor Management
Solution Architecture
Enterprise Software
E-commerce
Project Management
Software Development
IT Strategy
Strategic Planning
Strategy
Product Management
Leadership
ERP
Cross-functional Team Leadership
Project Planning
SDLC
Business Analysis
Integration
Vendor Management
Solution Architecture
Enterprise Software
Honor & Awards:
Recipient of Jane Robertson Memorial Award for Academic Excellence from the Kellogg School of Management, Northwestern University
Featured in the Dean's List at Kellogg School of Management, Northwestern Unversity
Awards:
Jane Robertson Award for Academic Excellence
Kellogg School Of Management
One of the 14 MBA students out of 1400 to receive the Jane Robertson Award for Academic Excellence for maintaining a perfect CGPA at Kellogg
Kellogg School Of Management
One of the 14 MBA students out of 1400 to receive the Jane Robertson Award for Academic Excellence for maintaining a perfect CGPA at Kellogg
Component Design Engineer At Intel Corporation
View pagePosition:
Component Design Engineer at Intel Corporation
Location:
Sacramento, California Area
Industry:
Electrical/Electronic Manufacturing
Work:
Intel Corporation since Aug 2008
Component Design Engineer
Intel Corporation Jun 2007 - Dec 2007
Component Design Engineer Intern
Component Design Engineer
Intel Corporation Jun 2007 - Dec 2007
Component Design Engineer Intern
Education:
Texas A&M University 2006 - 2008
Masters, Computer Engineering Anna University 2002 - 2006
B.E., Electronics & Communication Engineering
Masters, Computer Engineering Anna University 2002 - 2006
B.E., Electronics & Communication Engineering
Interests:
VLSI Design and Validation
Honor & Awards:
1. Received merit scholarship from the Department of ECE, Texas A&M University for 2006 and 2007.
2. Honor student at St.Joseph’s College of Engineering – 7th in department out of 135 students.
3. Undergraduate project was nominated for Indian Society for Academic Excellence Award.
Head Of Solution Architecture At Tesco Plc
View pagePosition:
Head of Solution Architecture at Tesco PLC
Location:
Bengaluru, Karnataka, India
Industry:
Retail
Work:
Tesco PLC - Bengaluru Area, India since Feb 2013
Head of Solution Architecture
Head of Solution Architecture
Education:
Northwestern University - Kellogg School of Management 2006 - 2009
MBA, Strategy, Finance and Marketing College of Engineering, Guindy
Indian Institute of Technology, Delhi
MBA, Strategy, Finance and Marketing College of Engineering, Guindy
Indian Institute of Technology, Delhi
Skills:
Enterprise Architecture
E-commerce
Project Management
Software Development
IT Strategy
Strategic Planning
Strategy
Product Management
Leadership
ERP
Cross-functional Team Leadership
Project Planning
SDLC
Business Analysis
Integration
Vendor Management
Solution Architecture
Enterprise Software
E-commerce
Project Management
Software Development
IT Strategy
Strategic Planning
Strategy
Product Management
Leadership
ERP
Cross-functional Team Leadership
Project Planning
SDLC
Business Analysis
Integration
Vendor Management
Solution Architecture
Enterprise Software
Honor & Awards:
Recipient of Jane Robertson Memorial Award for Academic Excellence from the Kellogg School of Management, Northwestern University
Featured in the Dean's List at Kellogg School of Management, Northwestern Unversity
Awards:
Jane Robertson Award for Academic Excellence
Kellogg School Of Management
One of the 14 MBA students out of 1400 to receive the Jane Robertson Award for Academic Excellence for maintaining a perfect CGPA at Kellogg
Kellogg School Of Management
One of the 14 MBA students out of 1400 to receive the Jane Robertson Award for Academic Excellence for maintaining a perfect CGPA at Kellogg
Business Records
Name / Title
Company / Classification
Phones & Addresses
President
ARMOR5, Inc., Which Will DO Business In California As ARMOR5 Software,Inc
650 Page Ml Rd, Palo Alto, CA 94304
401 Little Foot Dr, Fremont, CA 94539
401 Little Foot Dr, Fremont, CA 94539
Publications
Us Patents
Hybrid Pulse/Two-Stage Data Latch
View pageUS Patent:
20220345117, Oct 27, 2022
Filed:
Jul 12, 2022
Appl. No.:
17/812089
Inventors:
- Cupertino CA, US
Raghava Rao V. Denduluri - Cupertino CA, US
Ajay Bhatia - Saratoga CA, US
Suparn Vats - Fremont CA, US
Suresh Balasubramanian - Cupertino CA, US
Gopinath Venkatesh - San Jose CA, US
Teng Wang - Cupertino CA, US
Raghava Rao V. Denduluri - Cupertino CA, US
Ajay Bhatia - Saratoga CA, US
Suparn Vats - Fremont CA, US
Suresh Balasubramanian - Cupertino CA, US
Gopinath Venkatesh - San Jose CA, US
Teng Wang - Cupertino CA, US
International Classification:
H03K 3/037
G06F 1/28
G06F 1/08
G06F 1/28
G06F 1/08
Abstract:
An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
Hybrid Pulse/Two-Stage Data Latch
View pageUS Patent:
20200373915, Nov 26, 2020
Filed:
Aug 10, 2020
Appl. No.:
16/989621
Inventors:
- Cupertino CA, US
Raghava Rao V. Denduluri - Cupertino CA, US
Ajay Bhatia - Saratoga CA, US
Suparn Vats - Fremont CA, US
Suresh Balasubramanian - Cupertino CA, US
Gopinath Venkatesh - San Jose CA, US
Teng Wang - Cupertino CA, US
Raghava Rao V. Denduluri - Cupertino CA, US
Ajay Bhatia - Saratoga CA, US
Suparn Vats - Fremont CA, US
Suresh Balasubramanian - Cupertino CA, US
Gopinath Venkatesh - San Jose CA, US
Teng Wang - Cupertino CA, US
International Classification:
H03K 3/037
G06F 1/28
G06F 1/08
G06F 1/28
G06F 1/08
Abstract:
An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
Hybrid Pulse/Master-Slave Data Latch
View pageUS Patent:
20200106425, Apr 2, 2020
Filed:
Jan 9, 2019
Appl. No.:
16/243954
Inventors:
- Cupertino CA, US
Raghava Rao V. Denduluri - Cupertino CA, US
Ajay Bhatia - Saratoga CA, US
Suparn Vats - Fremont CA, US
Suresh Balasubramanian - Cupertino CA, US
Gopinath Venkatesh - San Jose CA, US
Teng Wang - Cupertino CA, US
Raghava Rao V. Denduluri - Cupertino CA, US
Ajay Bhatia - Saratoga CA, US
Suparn Vats - Fremont CA, US
Suresh Balasubramanian - Cupertino CA, US
Gopinath Venkatesh - San Jose CA, US
Teng Wang - Cupertino CA, US
International Classification:
H03K 3/037
G06F 1/08
G06F 1/28
G06F 1/08
G06F 1/28
Abstract:
An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
Systems And Methods For Improving Sales Process Workflow
View pageUS Patent:
20180101797, Apr 12, 2018
Filed:
Oct 10, 2017
Appl. No.:
15/729024
Inventors:
- San Jose CA, US
Thomas Eugene SAULPAUGH - San Jose CA, US
Jonathan Lee BRINK - San Jose CA, US
Suresh BALASUBRAMANIAN - Sunnyvale CA, US
Thomas Eugene SAULPAUGH - San Jose CA, US
Jonathan Lee BRINK - San Jose CA, US
Suresh BALASUBRAMANIAN - Sunnyvale CA, US
International Classification:
G06Q 10/06
G06Q 30/02
G06Q 30/02
Abstract:
Presented are systems and methods for analyzing a sales process workflow to increasing sales productivity. In embodiments, the system comprises a sales person activity recorder that monitors and records sales-related data according to one or more data categories from one or more data sources; a prospect activity recorder coupled to the sales person activity recorder, the prospect activity recorder monitors and records an interaction associated with a sales prospect; and an analytics processor coupled to the sales person activity recorder, the analytics processor synchronizes sales-related data from one or more data sources, and analyzes, based on at least the interaction, some or all of the data to obtain a result, the analytics processor generates and outputs, based on the analysis, a result that comprises at least one of a progress report, a ranking of prospects, and a sales performance score.