Sung Won Choi

8529876, Sep 10, 2013

Feb 14, 2012

13/396580

Sung Yuen Choi - Tarrytown NY, US

BASF Corporation - Florham Park NJ

A61K 8/00
A61K 8/18

424 69

Provided is a pigment composition comprising a first and second effect pigments, wherein the composition has a hue comparable to carmine but does not comprise carmine.

52610497, Nov 9, 1993

Jul 22, 1991

7/733906

Leon Lumelsky - Stamford CT
Sung M. Choi - White Plains NY

International Business Machines Corporation - Armonk NY

G06F 1520

395164

An image buffer semiconductor chip is described that includes circuitry for decompressing, compressed pixel image data such data comprising at least a pair of color codes and a bit mask including bit positions with values that define which pixels in a pixel subset of the pixel image receive the encoded color code data. The chip comprises a matrix of memory modules with the pixels in a pixel subset stored in an interleaved fashion, one pixel per module. A data bus communicates with all of the memory modules and broadcasts the color codes. A mask register stores the bit mask when it appears on the data bus. Circuitry selectively writes a first color code in the modules in accordance with bit values of a first kind in the MASK and writes the second color code into the modules in accordance with bit values of a second kind in the MASK.

52203123, Jun 15, 1993

Sep 29, 1989

7/414967

Leon Lumelsky - Stamford CT
Alan W. Peevers - Peekskill NY
Sung M. Choi - White Plains NY

International Business Machines Corporation - Armonk NY

G09G 128
H04N 974

340721

A locking mechanism is incorporated in a high-resolution video display system including a monitor, a computer for providing controls signals to said display system and two frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer. The output lock utilizes an extra bit-plane in the video buffer which stores a predetermined lock pattern and utilizes the normal monitor output port of the buffer operating under control of standard frame buffer addressing circuitry in combination with straight-forward combinational logic to achieve the locking function. The input lock utilizes a small DRAM which stores the input lock pattern data and utilizes this data in conjunction with normal write operations in the video buffer to control circuitry to disable the write function in predetermined regions of the video buffer.

49491695, Aug 14, 1990

Oct 27, 1989

7/428251

Leon Lumelsky - Stamford CT
Sung M. Choi - White Plains NY
Alan W. Peevers - Peekskill NY

International Business Machines Corporation - Armonk NY

H04N 710

358 86

An interface architecture for interconnecting a plurality of video display devices together over a high speed digital communication link having limited bandwidth provides at each node for transmitting during a "transmit mode"; (1) sequential pixels of digital data (COMVIDOUT) comprising separate luminance and chrominance fields, from a digital TV source associated with each display node which data represents a scaled video window, (2) the local system clock (SCLK), (3) vertical and horizontal communication sync signals (COMVSOUT and COMSHOUT), (4) luminance and chrominance clock enable signals (COMYOCE and COMCOCE) based on a scaling algorithm utilized in the transmitting video device to insure that both the proper pixels and the proper luminance and chrominance fields associated with these pixels are selected by the communications device for transmission. Further, the interface architecture at each display node provides for receiving during a "receive mode", (5) video input data pixels (COMVIDIN), (6) a video input data clock enable signal from the communications adapter (COMVINCE) which controls the storage of the received video data window in the local frame buffer, (7) horizontal and vertical video input sync signals from the communications adapter (COMHSIN and COMVSIN) for properly synchronizing the storing of the received video input data from the communications adapter into the frame buffer beginning ata predetermined address therein. The system utilizes, to a great extent, exisiting hardware in conventional video display device architectures and associated communications adapters such that a versatile generally applicable transmission system is achievable requiring a minimum of additional control hardware and software.

60880457, Jul 11, 2000

Jul 22, 1991

7/733950

Leon Lumelsky - Stamford CT
Sung Min Choi - White Plains NY
Alan Wesley Peevers - Berkeley CA
John Louis Pittas - Bethel CT

International Business Machines Corporation - Armonk NY

G09G 536

345509

An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer. Each of the 24-bit buffers store R,G,B pixel data and the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value.

54206081, May 30, 1995

Jan 27, 1994

8/187823

Sung M. Choi - White Plains NY
Leon Lumelsky - Stamford CT
Alan W. Peevers - Peekskill NY
John L. Pittas - Bethel CT

International Business Machines Corporation - Armonk NY

G09G 102

345186

A display system is described which includes storage for receiving a compressed pixel image manifesting at least a pair of encoded colors and a bit MASK that defines which pixels of a pixel subset of the pixel image receive one of the colors. The system comprises a plurality of memory modules. The pixels in the subset are interleaved in the memory modules. A generator is provided for applying signals to cause data to be written into each of modules in parallel. Register means are provided for applying data manifesting the encoded colors to the modules. Control apparatus is responsive to the MASK bits for controlling the generator to write the encoded color data, in parallel and in a single memory cycle, into all pixel positions of the subset that are designated for the color(s) by MASK bit position values.

53510674, Sep 27, 1994

Jul 22, 1991

7/733766

Leon Lumelsky - Stamford CT
Sung M. Choi - White Plains NY
Alan W. Peevers - Berkeley CA
John L. Pittas - Bethel CT

International Business Machines Corporation - Armonk NY

G09G 102
G09G 106

345191

Method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path is highly parallelized, and employs parallel devices operating under the control of a set of look-up tables. The look-up tables are loadable from a controller, such as a host workstation. The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats from a potentially large number of different sources. Outputs from several image sources are mixed under the control of the host workstation, with a resultant pixel value being based on (a) a combined translucency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation. Pixel value conversion to a common predetermined format provides coherency between pixel values generated by a number of different image sources, such as HDTV and graphics servers. A separate frame buffer is allocated for each of the sources.

51627795, Nov 10, 1992

Jul 22, 1991

7/733945

Leon Lumelsky - Stamford CT
Lawrence Cheng - Hastings-on-Hudson NY
Sung M. Choi - White Plains NY

International Business Machines Corporation - Armonk NY

G09G 302

340709

A stereoscopic sursor for high-resolution stereoscopic raster display is addressable to any arbitrary point on the display and simulates depth by alternately displaying left and right patterns that are offset from one another in a horizontal (x-axis) direction. Left and right views of the cursor are alternately displayed at the display frame rate, while a shutter mechanism presents the appropriate views to the viewer's eyes. To further enhance the perception of depth, monoscopic depth cues are provided by varying the cursor's color, size, transparency and/or pattern as the cursor moves in depth.