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Sara B Harrison

from Saint Rose, LA
Age ~67
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Also known as:
Sara Benaldra Harrison, Sarah B Harrison, Sara Robinson
Related to:
Mary RobinsonMarvin Winkfield, 79Rebecca Robinson, 50Charles Robinson, 70Catherine Robinson, 33
Connected to:
Aaron T Harrison, 67Ahmad K Harrison, 64Amir S Harrison, 38Andreas R Harrison, 48Angela Harrison, 43Angi Harrison, 45Antoine Harrison, 44Antwaan V Harrison, 37Ashley H Harrison, 45Ashlynn S Harrison, 30

Sara Harrison Phones & Addresses

  • Saint Rose, LA
  • New Orleans, LA
  • Redwood City, CA
  • Portland, TX
  • Hampton, VA
  • East Palo Alto, CA
  • Menlo Park, CA
  • San Francisco, CA

Work

Company: Sara "Cathi" Harrison Attorney at Law Address:

Professional Records

Lawyers & Attorneys

Sara Harrison Photo 1

Sara Harrison - Lawyer

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Office:
Sara "Cathi" Harrison Attorney at Law
ISLN:
918922494
Admitted:
2003
University:
Murray State University, B.A., 2000
Law School:
Southern Illinois University, J.D., 2003

Resumes

Resumes

Sara Harrison Photo 2

Sara Harrison

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Position:
Supply Network Operations Manager at Procter & Gamble Co
Location:
Cincinnati, Ohio
Industry:
Consumer Goods
Work:
Procter & Gamble Co - Cincinnati, OH since May 1998
Supply Network Operations Manager
Mettler-Toledo International, Inc - Columbus, Ohio Area Jun 1997 - Sep 1997
Engineering Associate
Copeland Corporation - Sidney, OH Mar 1995 - Dec 1996
Engineering Co-op Student
Education:
The Ohio State University 1994 - 1998
BS, Industrial & Systems Engineering St Ursula Academy 1989 - 1993
Skills:
Business Planning
Value Stream Mapping
Continuous Improvement
Supply Chain Optimization
Supply and Operations Planning (S&OP)
Distribution Management
SAP R/3
Demand Planning
Supply
Sales Plan
Cross-functional Team Leadership
Sara Harrison Photo 3

Sara Harrison

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Location:
United States
Sara Harrison Photo 4

Sara Harrison

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Location:
United States
Sara Harrison Photo 5

Sara Harrison

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Location:
United States
Sara Harrison Photo 6

Sara Harrison

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Location:
San Antonio, Texas
Industry:
Libraries
Work:
SEED School of Washington DC Sep 2008 - Jun 2011
Librarian
Blank Rome LLP Jan 2006 - Aug 2008
Acting Library Manager
Education:
The Catholic University of America 2006 - 2008
MLS, Library Science Brigham Young University 1999 - 2005
BA, English, TESOL
Sara Harrison Photo 7

Sara Harrison

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Location:
United States
Sara Harrison Photo 8

Associate Director, Human Resources At Novartis Vaccines And Diagnostics

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Position:
Associate Director, Human Resources at Novartis Vaccines and Diagnostics
Location:
Oakland, California
Industry:
Biotechnology
Work:
Novartis Vaccines and Diagnostics - Emeryville since Jan 2010
Associate Director, Human Resources
Doctors Medical Center - San Pablo Jan 2009 - Dec 2009
Manager of Employment
Seton Medical Center Jan 2000 - Jan 2009
Manager of Employment
Education:
Golden Gate University 2003 - 2004
Sara Harrison Photo 9

Sara Harrison

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Location:
United States

Publications

Isbn (Books And Publications)

Don Brown: Yoko

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Author

Sara Harrison

ISBN #

3883759236

Us Patents

Three Dimensional Vertically Structured Electronic Devices

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US Patent:
20210328057, Oct 21, 2021
Filed:
Apr 22, 2021
Appl. No.:
17/238012
Inventors:
- Livermore CA, US
Sara Elizabeth Harrison - Fremont CA, US
Rebecca Nikolic - Oakland CA, US
Qinghui Shao - Fremont CA, US
Lars Voss - Livermore CA, US
International Classification:
H01L 29/78
H01L 29/778
H01L 29/20
H01L 29/205
H01L 29/808
H01L 29/66
H01L 29/06
Abstract:
An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.

Three Dimensional Vertically Structured Electronic Devices

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US Patent:
20210159337, May 27, 2021
Filed:
Jan 7, 2021
Appl. No.:
17/143972
Inventors:
- Livermore CA, US
Sara Elizabeth Harrison - Fremont CA, US
Rebecca Nikolic - Oakland CA, US
Qinghui Shao - Fremont CA, US
Lars Voss - Livermore CA, US
International Classification:
H01L 29/78
H01L 29/778
H01L 29/20
H01L 29/205
H01L 29/808
H01L 29/66
H01L 29/06
Abstract:
In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.

Gallidation Assisted Impurity Doping

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US Patent:
20190393038, Dec 26, 2019
Filed:
Jun 19, 2019
Appl. No.:
16/446460
Inventors:
- Livermore CA, US
Daniel Max Dryden - Oakland CA, US
Clint Frye - Livermore CA, US
Sara Elizabeth Harrison - Fremont CA, US
Rebecca J. Nikolic - Oakland CA, US
Qinghui Shao - Fremont CA, US
International Classification:
H01L 21/225
H01L 29/20
H01L 29/207
H01L 21/324
Abstract:
In one embodiment, a product includes a structure comprising a material of a Group-III-nitride having a dopant, where a concentration of the dopant in the structure has a concentration gradient characteristic of diffusion of the dopant inward from at least a portion of a surface of the structure in a direction substantially normal to the portion of the surface. The structure has less than 1% decomposition of the Group-III-nitride at the surface of the structure.

Three Dimensional Vertically Structured Electronic Devices

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US Patent:
20170222047, Aug 3, 2017
Filed:
Jan 4, 2017
Appl. No.:
15/398652
Inventors:
- Livermore CA, US
Sara Elizabeth Harrison - Fremont CA, US
Rebecca J. Nikolic - Oakland CA, US
Qinghui Shao - Fremont CA, US
Lars Voss - Livermore CA, US
International Classification:
H01L 29/78
H01L 29/66
H01L 29/06
H01L 29/205
H01L 29/20
Abstract:
In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

Three Dimensional Vertically Structured Electronic Devices

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US Patent:
20170200820, Jul 13, 2017
Filed:
Jan 7, 2016
Appl. No.:
14/990612
Inventors:
- Livermore CA, US
Sara Elizabeth Harrison - Fremont CA, US
Rebecca Nikolic - Oakland CA, US
Qinghui Shao - Fremont CA, US
Lars Voss - Livermore CA, US
International Classification:
H01L 29/778
H01L 29/10
H01L 29/205
H01L 29/66
H01L 29/20
Abstract:
According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.

Capacitance Reduction For Pillar Structured Devices

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US Patent:
20160356901, Dec 8, 2016
Filed:
Nov 26, 2014
Appl. No.:
14/555463
Inventors:
- Livermore CA, US
Adam Conway - Livermore CA, US
Rebecca J. Nikolic - Oakland CA, US
Lars Voss - Livermore CA, US
Ishwara B. Bhat - Clifton Park NY, US
Sara E. Harrison - Fremont CA, US
International Classification:
G01T 3/08
H01L 31/117
Abstract:
In one embodiment, an apparatus includes: a first layer including a n+ dopant or p+ dopant; an intrinsic layer formed above the first layer, the intrinsic layer including a planar portion and pillars extending above the planar portion, cavity regions being defined between the pillars; and a second layer deposited on a periphery of the pillars thereby forming coated pillars, the second layer being substantially absent on the planar portion of the intrinsic layer between the coated pillars. The second layer includes an n+ dopant when the first layer includes a p+ dopant. The second layer includes a p+ dopant when the first layer includes an n+ dopant. The apparatus includes a neutron sensitive material deposited between the coated pillars and above the planar portion of the intrinsic layer. In additional embodiments, an upper portion of each of the pillars includes a same type of dopant as the second layer.
Control profile
Sara B Harrison from Saint Rose, LA, age ~67 Get Report