Robert W Reilly

41646282, Aug 14, 1979

Mar 17, 1978

5/887708

Charles R. Ward - Passaic NJ
Robert A. Reilly - North Caldwell NJ

International Telephone and Telegraph Corporation - Nutley NJ

H04J 1300

179 15BA

This relates to a signal processor which accepts the linear sum of several continuous (CW) direct sequence, spread spectrum signals, and outputs a sequence of narrow pulses, each of which contains all the available energy of one of the input signals. The CW signals are applied to the input of a tapped delay line, the contents of which are compared, in a parallel fashion, with the output of a code storage register. When correlation has been achieved, a narrow pulse is produced which contains all the available energy of one of the input signals. The circuit reduces the problem of continuously processing several simultaneous signals, conventionally performed with dedicated circuitry for each signal, to a sequential pulse processing operation, effectively timesharing the same single set of circuitry. Both amplitude and phase information is preserved through the processing technique allowing implementation in coherent and non-coherent system architectures.

41422406, Feb 27, 1979

Aug 31, 1977

5/829382

Charles R. Ward - Passaic NJ
Robert A. Reilly - North Caldwell NJ

International Telephone & Telegraph Corp. - Nutley NJ

G06F 700

364717

The code generator of the present invention uses digital memories to replace the linear feedback shift registers of the prior art. Each memory contains the time ordered bit sequence for each of the component codes which in general, make up the overall, longer code. Since the entire bit sequences of the component codes are immediately available in the memories by appropriate addressing, the code generator can be initialized to an arbitrary, but defined code state within the response time of the memory element. As an additional benefit, at the option of the designer, the digital memory can be chosen to extract code segments, for example, 8 bits wide rather than single bits, and this parallel approach reduces code clocking speed through much of the code generator hardware, and/or may permit several code patterns for multichannel applications to be constructed using the same common memories.