Richard D Sanders

7080284, Jul 18, 2006

Jul 19, 2002

10/199938

Josef Zeevi - Austin TX, US
Richard Lee Sanders - Hutto TX, US

Newisys, Inc. - Austin TX

G06F 11/00

714 31, 714 46

A computer server architecture and diagnostic framework for testing same is described. The diagnostic infrastructure consists of various logical modules present on both service processor-side and platform-side regions of a server. These modules work together to present a modular, extensible yet unitary diagnostic framework. The invention permits dynamic operation of information resources, and extensibility when/if expansion is needed. The server architecture includes an OS independent, custom ASIC and processors configured in a 4-way geometry which permits scalable expansion up to a 16-way configuration geometry within a SMP programming model. The server architecture is capable of integration with third party management frameworks, for example, SNMP and CIM, and is modularly scalable, i. e. , offers a “one to many” management capability. The server architecture is capable of both 32-bit and 64-bit computing, and the 64-bit computing ability is 32-bit application backward compatible, offering the advantage of a non-disruptive migration to 64-bit computing.

7395401, Jul 1, 2008

Sep 30, 2005

11/241299

Richard Sanders - Hutto TX, US
Josef Zeevi - Austin TX, US

Sigmatel, Inc. - Austin TX

G06F 12/00

711170

The disclosure is directed to a method of determining memory parameters of a memory device. The method includes determining a communication protocol associated with the memory device, determining a page size of the memory device by using the communication protocol to communicate a page of data, determining a block size of the memory device by using the communication protocol to erase a block of the memory device, and determining a capacity of the memory device by using the communication protocol to determine a number of significant address bits.

7594087, Sep 22, 2009

Jan 19, 2006

11/335292

Josef Zeevi - Austin TX, US
Grayson Dale Abbott - Pflugerville TX, US
Richard Sanders - Hutto TX, US
Glenn Reinhardt - Austin TX, US

Sigmatel, Inc. - Austin TX

G06F 13/00

711165, 711 3, 711110, 711112, 711169

A method and system for accessing a non-volatile memory is disclosed. The method includes writing a first stream of data to a first block of a first region of a non-volatile memory and detecting a full condition of the first block of the first region. Further, the method includes identifying data to be copied from the first block of the first region and copying the identified data from the first block of the first region to a second block of the first region of the non-volatile memory. The method also includes writing a second stream of data to the second block of the first region and writing a third stream of data to a first block of a second region of the non-volatile memory. In addition, the method includes detecting a full condition of the first block of the second region, identifying data to be copied from the first block of the second region and copying the identified data from the first block of the second region to a second block of the second region of the non-volatile memory. The method also includes writing a fourth stream of data to the second block of the second region of the non-volatile memory.

7627712, Dec 1, 2009

Mar 22, 2005

11/085967

Richard Sanders - Hutto TX, US
Josef Zeevi - Austin TX, US

Sigmatel, Inc. - Austin TX

G06F 12/00

711103, 711 4, 711 5, 711100, 711102, 711156, 711157, 711200, 711202, 711203, 365189011, 36518904, 36523001, 36523003, 36523004

A computational system comprising a controller and a multi-plane solid state memory device accessible to the controller is disclosed. The controller is configured to provide access to a virtual block having a virtual block address that represents a first block from a first plane of the multi-plane solid state memory device and represents a second block from a second plane of the multi-plane solid state memory device.

7644251, Jan 5, 2010

Dec 19, 2005

11/312852

Richard Sanders - Hutto TX, US
David C. Baker - Austin TX, US

Sigmatel, Inc. - Austin TX

G06F 9/26
G06F 9/34
G06F 13/00
G06F 13/28

711203, 711103

A controller includes a volatile random access memory and translation hardware. The volatile random access memory includes a table having at least one entry. The at least one entry includes a portion of a physical address of a memory location at a NAND flash non-volatile solid-state memory. The volatile random access memory is accessible to the translation hardware. The translation hardware is configured to sum binary data bits of a portion of a logical address and a pointer value to determine a random access memory address of the at least one entry and is configured to determine the portion of the physical address of the memory location at the NAND flash non-volatile solid-state memory based at least in part on the random access memory address of the at least one entry.

7685333, Mar 23, 2010

Mar 22, 2005

11/085995

Richard Sanders - Hutto TX, US

Sigmatel, Inc - Austin TX

G06F 3/01
G06F 13/00
G06F 11/36

710 33, 710 62, 710 12, 710 15

A computational system is disclosed. The computational system includes a controller having a table including a plurality of sets of timing parameters. The plurality of sets of timing parameters are ordered based on a speed rate. The computational system also includes a device accessible to the controller. The controller communicates with the device in accordance with one set of timing parameters selected from the plurality of sets of timing parameters.

20060069896, Mar 30, 2006

Sep 27, 2004

10/952587

Richard Sanders - Hutto TX, US

G06F 12/00

711168000, 711103000

The disclosure is directed to a system including a first flash memory device having a first interface and a first control interface that includes a first chip enable control input, a second flash memory device having a second interface and a second control interface that includes a second chip enable control input, and a controller that includes a data output and a control signal output. A first portion of the data output is coupled to the first interface. A second portion of the data output is coupled to the second interface. The control signal output includes a chip enable output coupled to both the first chip enable control input and the second chip enable control input. The first flash memory device and the second flash memory device are both configured to concurrently receive input data communicated to the first interface and the second interface from the data output.

20070076478, Apr 5, 2007

Sep 30, 2005

11/240581

Richard Sanders - Hutto TX, US

SigmaTel, Inc. - Austin TX

G11C 16/04

365185110

The disclosure is directed to a method of managing data storage. The method includes detecting an unusable memory block. The unusable memory block is in a set of user accessible memory blocks of a memory device. The memory device includes the set of user accessible memory blocks, a set of defective memory blocks, and a set of replacement memory blocks. The set of user accessible memory blocks includes not more than one half of a total number of memory blocks of the memory device and includes memory blocks from both halves of the memory device as addressed by a significant address bit. The method also includes indicating that the unusable memory block is a defective memory block and includes allocating a replacement memory block from the set of replacement memory blocks to the set of user accessible memory blocks.