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Pradeep F Pandey

from San Jose, CA
Age ~66
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Also known as:
Pradeep E Pandey, Pradeep P Pandey
Phone and address:
7169 Brooktree Ct, San Jose, CA 95120
(408) 927-7369
Related to:
Arpit D Pandey, 40Albert N Baeza, 57Irma S Keith, 51Robert Baeza, 39Richard Rodriguez, 69Deanna Avila, 36
Connected to:
Abhilasha Pandey, 54Adarsha R Pandey, 43Aishwarya Pandey, 44Ankita Pandey, 30Anne E Pandey, 56Archit Pandey, 43Bal R Pandey, 49Basu R Pandey, 44Bhartendu Pandey, 36

Pradeep Pandey Phones & Addresses

  • 7169 Brooktree Ct, San Jose, CA 95120 (408) 927-7369 (408) 927-7600
  • Sunnyvale, CA
  • Provo, UT
  • 7169 Brooktree Ct, San Jose, CA 95120

Work

Position: Executive, Administrative, and Managerial Occupations

Education

Degree: High school graduate or higher

Resumes

Resumes

Pradeep Pandey Photo 1

Founder & Cto, Gelina, Inc.

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Position:
Founder and CTO at Gelina, Inc.
Location:
San Jose, California
Industry:
Computer Software
Work:
Gelina, Inc. - San Jose, CA since Mar 2003
Founder and CTO
EcoFactor - Redwood City, CA Mar 2010 - Sep 2011
Director, R&D
TiE Silicon Valley - Santa Clara, CA Jan 2006 - Dec 2009
Board of Directors
Startups Jan 2001 - Dec 2009
Business Advisor
IP Unity - Milpitas, CA May 2001 - Feb 2003
Sr. Director, Business Development
Education:
University of California, Santa Barbara 1986 - 1990
Ph.D., Electrical Engineering Duke University 1979 - 1980
M.S. Indian Institute of Technology, Delhi 1974 - 1979
B. Tech.
Skills:
Strategic Partnerships
Start-ups
Business Strategy
Innovation
Entrepreneurship
Analytics
Big Data
Strategic Consulting
Product Management
Go-to-market Strategy
Consulting
Telecommunications
Honor & Awards:
Awarded 18 patents
Pradeep Pandey Photo 2

Pradeep Pandey

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Location:
United States
Pradeep Pandey Photo 3

Pradeep Pandey

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Location:
United States
Pradeep Pandey Photo 4

Pradeep Pandey

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Location:
United States
Pradeep Pandey Photo 5

Pradeep Pandey

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Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Pradeep Pandey
President
GELINA, INC
Business Services at Non-Commercial Site
7169 Brooktree Ct, San Jose, CA 95120

Publications

Isbn (Books And Publications)

Banking Reforms and Globalisation

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Author

Pradeep Kumar Pandey

ISBN #

8131301591

Us Patents

Reduction Of Switching Transients Via Large Signal/Small Signal Thresholding

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US Patent:
6452291, Sep 17, 2002
Filed:
Jul 1, 1999
Appl. No.:
09/348883
Inventors:
Mark Erickson - Sunnyvale CA
Thorkell Gudmundsson - San Jose CA
Pradeep Pandey - San Jose CA
Assignee:
Voyan Technology - Santa Clara CA
International Classification:
F02D 3100
US Classification:
307131, 703 94, 180170
Abstract:
The present invention includes a method and system for reducing switching transients via large signal/small signal thresholding. The present invention prevents a switch from occurring if when the system (i. e. , the system under control) is in small signal mode and permits switches to occur when the system is in large signal mode. Large signal and small signal modes are determined by comparing the difference between the most current value of a comparator variable and the final setpoint with a threshold distance. The system is in small signal mode if the most current value of the comparator variable less the final setpoint value is less than the threshold distance. Otherwise, the system is in large signal mode.

Batch Type Heat Treatment System, Method For Controlling Same, And Heat Treatment Method

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US Patent:
6730885, May 4, 2004
Filed:
Jul 5, 2001
Appl. No.:
09/897908
Inventors:
Fujio Suzuki - Tokyo-To, JP
Wenling Wang - Tokyo-To, JP
Koichi Sakamoto - Tokyo-To, JP
Moyuru Yasuhara - Tokyo-To, JP
Sunil Shah - Los Altos CA
Pradeep Pandey - San Jose CA
Assignee:
Tokyo Electron Limited - Tokyo-To
International Classification:
H05B 302
US Classification:
219486, 392416
Abstract:
There is provided a batch type heat treatment system, control method and heat treatment method capable of appropriately coping with a multi-product small-lot production. A reaction tube comprises a plurality of heaters through and a plurality of temperature sensors, and houses therein a wafer boat A control part stores therein many mathematical models for estimating (calculating) the temperature of wafers W in the reaction tube in accordance with the number and arranged position of the wafers W mounted on the wafer boat and many target temperature trajectories. If the wafer boat is loaded in the reaction tube a mathematical model and a target temperature trajectory corresponding to the number and arranged position of the mounted wafers W are read. If a deposition process is started, the output of a temperature sensor S and the model are used for estimating the temperature of the wafers W in the reaction tube and the powers to be supplied to the heaters through are separately controlled so that the estimated temperature approaches the target temperature trajectory.

Batch-Type Heat Treatment Apparatus And Control Method For The Batch-Type Heat Treatment Apparatus

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US Patent:
6803548, Oct 12, 2004
Filed:
Sep 13, 2001
Appl. No.:
09/950876
Inventors:
Wenling Wang - Tokyo-To, JP
Koichi Sakamoto - Tokyo-To, JP
Fujio Suzuki - Tokyo-To, JP
Moyuru Yasuhara - Tokyo-To, JP
Sunil Shah - Los Altos CA
Pradeep Pandey - San Jose CA
Mark Erickson - Sacramento CA
Assignee:
Tokyo Electron Limited - Tokyo-To
International Classification:
H05B 102
US Classification:
219494, 219497
Abstract:
A heat treatment apparatus for making a heat treatment while estimating temperatures of objects-to-be-processed that can estimate correct temperatures of the objects-to-be-processed. A reaction tube includes heaters and temperature sensors, and receives a wafer boat. A controller estimates temperatures of wafers and temperatures of the temperature sensors in zones in the reaction tube corresponding to the heaters by using the temperature sensors and electric powers of the heaters. Based on relationships between estimated temperatures of the temperature sensors and really metered temperatures, functions expressing the relationships between the estimated temperatures and the really metered temperatures are given for the respective zones. The functions are substituted by the estimated wafer temperatures to correct the estimated wafer temperatures. Electric powers to be fed to the respective heaters are respectively controlled so that the corrected wafer temperatures are converged to target temperature trajectories.

Adaptive Real Time Control Of A Reticle/Mask System

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US Patent:
7025280, Apr 11, 2006
Filed:
Jan 30, 2004
Appl. No.:
10/769623
Inventors:
Sanjeev Kaushal - Austin TX, US
Pradeep Pandey - San Jose CA, US
Kenji Sugishima - Tokyo, JP
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
G06F 7/66
G06F 17/50
C23C 16/00
H05B 3/02
US Classification:
236 16, 700121, 118 501, 118725, 219483, 716 19
Abstract:
An adaptive real time thermal processing system is presented that includes a multivariable controller. Generally, the method includes creating a dynamic model of the thermal processing system; incorporating reticle/mask curvature in the dynamic model; coupling a diffusion-amplification model into the dynamic thermal model; creating a multivariable controller; parameterizing the nominal setpoints into a vector of intelligent setpoints; creating a process sensitivity matrix; creating intelligent setpoints using an efficient optimization method and process data; and establishing recipes that select appropriate models and setpoints during run-time.

Methods For Adaptive Real Time Control Of A Thermal Processing System

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US Patent:
7101816, Sep 5, 2006
Filed:
Dec 29, 2003
Appl. No.:
10/747842
Inventors:
Sanjeev Kaushal - Austin TX, US
Kenji Sugishima - Tokyo, JP
Pradeep Pandey - San Jose CA, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
G06F 19/00
US Classification:
438795, 700109, 700110, 700121, 73760
Abstract:
Methods for adaptive real time control of a system for thermal processing substrates, such as semiconductor wafers and display panels. Generally, the method includes creating a dynamic model of the thermal processing system, incorporating wafer bow in the dynamic model, coupling a diffusion-amplification model into the dynamic thermal model, creating a multivariable controller, parameterizing the nominal setpoints, creating a process sensitivity matrix, creating intelligent setpoints using an efficient optimization method and process data, and establishing recipes that select appropriate models and setpoints during run-time.

Media Flow Method For Transferring Real-Time Data Between Asynchronous And Synchronous Networks

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US Patent:
7126957, Oct 24, 2006
Filed:
Mar 7, 2002
Appl. No.:
10/094232
Inventors:
Sridhar G. Sharma Isukapalli - Fremont CA, US
Pradeep Pandey - San Jose CA, US
Matthew D. Shaver - Fremont CA, US
Neal A. Schneider - Palo Alto CA, US
Gary Tsztoo - Saratoga CA, US
Assignee:
UTStarcom, Inc. - Alameda CA
International Classification:
H04L 12/56
H04J 3/06
US Classification:
370412, 370429, 370516, 375371, 711200
Abstract:
A system for transmitting real-time data between an asynchronous network () and a synchronous network () is disclosed. A method () may include an ingress path () for transmitting data from an asynchronous system () to a synchronous system (), and an egress path () for transmitting data from a synchronous system () to an asynchronous system (). An ingress path () may include a packet receiver () and write to synchronous system () steps. An egress path () may include read from synchronous system (), packetizer (), and packet transmitter () steps.

Built-In Self Test For A Thermal Processing System

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US Patent:
7165011, Jan 16, 2007
Filed:
Sep 1, 2005
Appl. No.:
11/217230
Inventors:
Sanjeev Kaushal - Austin TX, US
Pradeep Pandey - San Jose CA, US
Kenji Sugishima - Tokyo, JP
Anthony Dip - Cedar Creek TX, US
David Smith - Cedar Creek TX, US
Raymond Joe - Austin TX, US
Sundar Gandhi - Austin TX, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
G06F 11/30
G06F 15/00
US Classification:
702182, 702183, 702185
Abstract:
A method of monitoring a thermal processing system in real-time using a built-in self test (BIST) table that includes positioning a plurality of wafers in a processing chamber in the thermal processing system; executing a real-time dynamic model to generate a predicted dynamic process response for the processing chamber during the processing time; creating a first measured dynamic process response; determining a dynamic estimation error using a difference between the predicted dynamic process response and the measured dynamic process response; and comparing the dynamic estimation error to operational thresholds established by one or more rules in the BIST table.

Monitoring A System During Low-Pressure Processes

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US Patent:
7302363, Nov 27, 2007
Filed:
Mar 31, 2006
Appl. No.:
11/278379
Inventors:
Sanjeev Kaushal - San Jose CA, US
Pradeep Pandey - San Jose CA, US
Kenji Sugishima - Tokyo, JP
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
G06F 11/30
US Classification:
702183
Abstract:
A method of monitoring a processing system in real-time using low-pressure based modeling techniques that include processing one or more of wafers in a processing chamber; determining a measured dynamic process response for a rate of change for a process parameter; executing a real-time dynamic model to generate a predicted dynamic process response; determining a dynamic estimation error using a difference between the predicted dynamic process response and the expected process response; and comparing the dynamic estimation error to operational limits.
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Pradeep F Pandey from San Jose, CA, age ~66 Get Report