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Phuc Huynh Do

from Elk Grove, CA
Age ~53
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Also known as:
Phuc H Do, Phuc H Huynh, Phuc T Huynh
Related to:
Tieutue T Duong, 48Trung Quach, 72Phoung T Do, 73Hien M Vo, 64Prunt VoLien T Nguyen, 89Trung Ung Do, 57Giung L Do
Connected to:
Allison Do, 40Andrea K Do, 54Ban V Do, 73Bibi P Do, 63Bobo D Do, 46Camille N Do, 62Cara L Do, 60Carole Do, 33Caroline J Do, 43Chan T Do, 61

Phuc Do Phones & Addresses

  • Elk Grove, CA
  • Oakland, CA
  • Plano, TX
  • Tampa, FL
  • Orlando, FL
  • Garden Grove, CA

Professional Records

Medicine Doctors

Phuc Do Photo 1

Phuc Tuan Huynh DO

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Specialties:
Emergency Medicine
Family Medicine
Education:
Michigan State University College of Osteopathic Medicine (1998)
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Phuc Kim Hoang Nguyen DO

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Specialties:
Emergency Medicine
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Phuc Hong Nguyen DO

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Specialties:
Emergency Medicine
Education:
Kansas City University of Medicine (2008)

Resumes

Resumes

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Phuc Do

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Phuc Do Photo 5

Mts Test Hardware Development Eng At Spansion

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Location:
San Francisco Bay Area
Industry:
Semiconductors
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Phuc Do

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Location:
United States
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Phuc Do

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Publications

Us Patents

Multi-Layered Pin Grid Array Interposer Apparatus And Method For Testing Semiconductor Devices Having A Non-Pin Grid Array Footprint

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US Patent:
6344684, Feb 5, 2002
Filed:
Jul 6, 2000
Appl. No.:
09/610865
Inventors:
Rafiqul Hussain - Fremont CA
Phuc Dinh Do - Santa Clara CA
Benjamin G. Tubera - Milpitas CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2348
US Classification:
257697, 257690, 257692, 257693, 361760, 361764, 324755, 439 71, 439 74
Abstract:
A multi-layered pin grid array interposer used in a test socket for testing and converting a package having a non-pin grid array footprint to a pin grid array footprint. The multi-layered pin grid array interposer test socket includes a multi-layered pin grid array interposer, a semiconductor device mounted on a package having a non-grid array footprint and a fastener. The multi-layered pin grid array interposer includes a top signal layer having bonding pads on an upper surface, a bottom signal layer having a pin grid array footprint on a bottom surface, at least one power layer between ground layers, the ground layers being between the top signal layer and bottom signal layer, and a links for connecting the plurality of bonding pads to the pins of the pin grid array footprint. The fastener presses the package against the multi-layered pin grid array interposer connecting the leads of the package with the bonding pads.
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Phuc Huynh Do from Elk Grove, CA, age ~53 Get Report