Peter Cases Yu

6484065, Nov 19, 2002

Oct 5, 1998

09/166498

Peter K. Yu - Sunnyvale CA
Michael D. Rostoker - Boulder Creek CA

Kawasaki Microelectronics, Inc. - Chiba

G06F 1900

700121, 700 2, 700 4, 700 5, 700117, 711105, 711112, 716 2, 716 3, 716 4, 365149, 36523003, 712 1, 712 10, 712 16

An efficient DSP or MPU is combined with efficient DRAM on a single IC die. To optimize the embedded memory, the chip includes wide-band connections to DRAM. Row and column addresses of DRAM can be applied at the same time using wide address busses. Additional metal lines lower the resistance of the word line in the DRAM circuits. For certain process steps, the processor block is masked off and the process steps unique to the fabrication of memory are performed on the memory block, and vice-versa. Process steps which are common to the processor and memory blocks can be performed simultaneously on the processor and memory blocks without masking off either block. Certain process steps can be employed in the fabrication of the one of the two processor and memory blocks in addition to or in lieu of processes normally used in the fabrication of that block. An electronic component (e. g. , integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

54086744, Apr 18, 1995

Dec 23, 1992

7/995772

Christopher I. W. Norrie - San Jose CA
Carolee N. Newcomb - Los Altos CA
Peter K. Yu - Sunnyvale CA

Amdahl Corporation - Sunnyvale CA

G06F 932
G06F 928

395800

A mapping system for mapping a plurality of two byte operation code series into a control store where in each two byte operation code the first byte identifies the series in which that two byte operation code is included and the second byte identifies that specific operation code within the identified series, the mapping system comprising a first register for storing the first and second bytes of a two byte operation codes, a first control store for storing control word for the two byte operation codes, a first means for generating, from the first and second bytes stored in the first register, a first control store address for the first control store thereby providing access to the control word for processing the two byte operation code store in the first register and a second means for generating, from the first and second bytes stored in the first register, a first signal when an invalid two byte operation code has been stored in the first register for processing, the first signal invalidating the processing of the two byte operation code stored in the first register including any processing of the control word accessed by the first control store in response to the first control store address generated by the first means.

53865499, Jan 31, 1995

Nov 19, 1992

7/978829

Christopher I. W. Norrie - San Jose CA
Carolee V. Newcomb - Los Altos CA
Peter K. Yu - Sunnyvale CA
Allan Zmyslowski - Sunnyvale CA

Amdahl Corporation - Sunnyvale CA

H03M 1300

395575

An error recovery system used in a pipeline architecture type computer system for recovering from an error in a control word for an instruction without interrupting the sequence of processing control words by the computer system. The computer system processes instructions in a sequence of overlapping FLOWs where each FLOW is comprised of a sequence of cycles. An instruction control word is processed in each cycle of each FLOW. The error recovery system comprises a first storage for storing, for a given cycle of a FLOW, all the control words for all the instructions, a second storage for storing a control word read from the first storage and an error recovery logic for detecting an error in the control word read from the first storage and stored in the second storage and for correcting the error in the control word in the first and second storage.