Mark Ross

6374326, Apr 16, 2002

Oct 25, 1999

09/426574

Arvind K. Kansal - Cupertino CA
Mark A. Ross - San Carlos CA
Sachidanandan Sambandan - Sunnyvale CA

Cisco Technology, Inc. - San Jose CA

G06F 1200

711108, 711 5, 711168, 365 49, 36523003, 370392

Content-addressable memory (CAM) architectures and methods of use are disclosed for enabling multiple concurrent lookups within a CAM array. One implementation arranges CAM arrays into multiple banks and enables parallel lookups of multiple key strings in multiple CAM banks. For a given input key, simultaneous parallel lookups in a plurality of CAM banks are performed by each bank using a bank key consisting of a subset of the bits of the input key. The multiple bank CAM is instructed to extract one or more distinct subsets of input key bits for use as bank lookup keys. Each bank key is passed to the appropriate bank according to the instruction received. Multiple bank sizes, depending on the key width and overall size of the CAM array, are also possible. Each bank produces a single output result, and each bank is returned to the host device that initially issued the lookup instruction.

6389506, May 14, 2002

Aug 7, 1998

09/130890

Mark Ross - San Jose CA
Andreas V. Bechtolsheim - San Jose CA

Cisco Technology, Inc. - San Jose CA

G06F 1200

711108, 365 49

A method and system for flexible matching of data in a CAM that does not use the overhead of one mask bit for each matched value bit. The entries of the CAM are logically grouped in a set of blocks, each block having a single mask that applies to all entries in the block. Each block includes a predetermined number of CAM entries, such as a block of 16 entries. However, in alternative embodiments, the number of CAM entries for each block could be predetermined to be a different number, or could be dynamically selected with the values that are entered into the CAM.

6526474, Feb 25, 2003

Nov 9, 1999

09/437012

Mark A. Ross - San Carlos CA

Cisco Technology, Inc. - San Jose CA

G06F 1208

711108, 711158

The invention provides a method and system for operating a CAM with a variable size input tag. The improved CAM has multiple access sizes and is divided into multiple stored match sections. Each of the multiple stored match sections can be independently matched against a portion of the input tag, responsive to a type field for each entry. A size selection circuit accumulates the independent match results; a priority encoder coupled thereto collects the accumulated matches and presents a match as an output from the CAM. Each CAM entry can be selected from a set of preselected sizes, each corresponding to a contemplated input tag size, such as 72 bits, 144 bits, or 288 bits.

6535951, Mar 18, 2003

Feb 29, 2000

09/515578

Mark A. Ross - San Carlos CA

Cisco Technology, Inc. - San Jose CA

G06F 1202

711108, 711103, 711151, 711154

The invention provides a method and system for performing additional processing on CAM hit results, in which the additional processing does not add to the complexity or size of the CAM chip, can be altered after manufacture of the CAM chip, and does not delay other operations of the CAM. The CAM hit results are presented as indices from the CAM and sent to a hit result register file where they are stored. The contents of the hit result register file can be processed by other hardware or software coupled to the CAM. The index associated with the CAM input tag can be accessed using the hit result register file and a register indirect operation. The index associated with the CAM input tag can be used for CAM management functions in conjunction with (such as in parallel or pipelined) other CAM functions.

6658002, Dec 2, 2003

Jun 17, 1999

09/335800

Mark A. Ross - San Carlos CA
Sun-Den Chen - San Jose CA
Andreas V. Bechtolsheim - Incline Village NV

Cisco Technology, Inc. - San Jose CA

H04L 1256

370392

An apparatus and method for performing logical operations on information in the communications protocol stack, such as the transport layer (L4) port numbers, characterizing a received packet or frame of data in a data communications device such as a router or switch. The results of the logical operations, along with other packet/frame-identifying data, are used to generate a more efficient lookup key. A content addressable memory (CAM) lookup is used to determine the action indicated by the rules defined by a rule-based routing or switching scheme, such as an access control list (ACL). The results of these logical operations extend the key space and thus provide a finer-grained match between the original, unextended input key and a rule action, thereby pointing to a rule action precisely tailored to packet processing. The rule can thus be applied with fewer CAM entries, providing the versatility improvement and CAM cost reduction necessary to keep up with the ever-increasing rule complexity requirements of advanced data communication and internetworking systems. An embodiment utilizing asymmetrical processing of packets, depending on whether the packet is inbound to the data communications device or outbound from it, is also disclosed.

6738862, May 18, 2004

Apr 29, 2002

10/135711

Mark A. Ross - San Carlos CA
Andreas V. Bechtolsheim - Woodside CA

Cisco Technology, Inc. - San Jose CA

G06F 1200

711108, 365 49

The invention provides a method and system for flexible matching of data in a CAM, that does not use the overhead of one mask bit for each matched value bit. The entries of the CAM are logically grouped in a set of blocks, each block having a single mask that applies to all entries in the block. Each block includes a predetermined number of CAM entries, such as a block of 16 entries. However, in alternative embodiments, the number of CAM entries for each block could be predetermined to be a different number, or could be dynamically selected with the values that are entered into the CAM.

7260673, Aug 21, 2007

Jul 20, 2001

09/910227

Mark A. Ross - San Carlos CA, US

Cisco Technology, Inc. - San Jose CA

G06F 12/00

711108, 365 49, 714 6

Methods and apparatus are disclosed for verifying the integrity of an index or result produced by a content-addressable or associated memory or other device. A pre-computed data protection field is stored, either as part of a returned index of a content-addressable memory or in a separate storage. In one implementation, a data protection operation is performed on all or part of the returned index and a comparison is made with a pre-computed data protection field. In one implementation, a copy of the masks employed by a ternary content-addressable memory and a set of pre-computed data protection fields are stored. A particular mask and pre-computed data protection field are selected based on the generated index. The original input value is then masked by the selected mask and provided to a data protection function. The result of this function is then compared to the selected pre-computed data protection field.

7343510, Mar 11, 2008

Dec 21, 2004

11/019731

Mark Ross - San Carlos CA, US
S. Babar Raza - San Jose CA, US
Dimitris Pantelakis - Austin TX, US
Anup Nayak - Fremont CA, US
Walter Bridgewater - San Jose CA, US

Cypress Semiconductor Corporation - San Jose CA

G06F 1/12

713500, 713400, 713502, 713503, 327 1, 327 48, 331 11

A clock detection and selection circuit () can include a first counter (-) that generates a first count value CNT according to a first clock signal CLK and a second counter (-) that generates a second count value CNT according to a second clock signal CLK. First separation-detect logic (-) and second separation-detect logic (-) determine if a pre-specified difference exists between a first count value (CNT/CNT′) and second count value (CNT/CNT′). According to such determinations, separation information (INF and INF) can be generated indicating which clock signal (CLK or CLK) is faster. Selection logic () can select a faster of the clock signals (CLK or CLK) if the separation information values confirm one another.