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Koichi Okamoto Phones & Addresses

  • Rolling Hills Estates, CA
  • 16514 Haas Ave, Torrance, CA 90504
  • Newport Beach, CA
  • Laguna Niguel, CA
  • Redondo Beach, CA
  • Los Angeles, CA
  • 8 Minori, Laguna Niguel, CA 92677 (310) 530-5677

Publications

Amazon

Keiri de tsukau eibun meru : Nichijo gyomu kara kessan zeimu shinkoku made.

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Author

Koichi Okamoto; Okamoto ando kanpani kokusai kaikei jimusho.

Binding

Tankobon Hardcover

Publisher

Chuokeizaisha.

ISBN #

4502488100

EAN Code

9784502488108

ISBN #

6

Chokkan o kagaku suru : Sono miezaru mekanizumu.

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Author

David G Myers; Koichi Okamoto

Binding

Tankobon Hardcover

Publisher

Reitakudaigakushuppankai : Hiroikegakuenjigyobu.

ISBN #

4892056111

EAN Code

9784892056116

ISBN #

5

Yuniku-sa no shakai shinrigaku: Ninchi keiseiteki apurochi to dokujisei yokkkyu tesuto (Japanese Edition)

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Author

Koichi Okamoto

Binding

Tankobon Hardcover

Pages

219

Publisher

Kawashima Shoten

ISBN #

4761004592

EAN Code

9784761004590

ISBN #

4

Ichiokunin no chado koza kokoro o tagayasu.

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Author

Koichi Okamoto

Binding

Tankobon Hardcover

Publisher

Tankosha.

ISBN #

4473040224

EAN Code

9784473040220

ISBN #

3

Nihonjin no YES wa naze NO ka?: Shakai shinrigakusha ga mita kono kuni no fushigi (Japanese Edition)

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Author

Koichi Okamoto

Binding

Hardcover

Pages

229

Publisher

PHP Kenkyujo

ISBN #

4569540449

EAN Code

9784569540443

ISBN #

2

Us Patents

Nitride Semiconductor Device And A Process Of Manufacturing The Same

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US Patent:
6876009, Apr 5, 2005
Filed:
Dec 9, 2002
Appl. No.:
10/314444
Inventors:
Yukio Narukawa - Anan, JP
Isamu Niki - Anan, JP
Axel Scherer - Pasadena CA, US
Koichi Okamoto - Pasadena CA, US
Yoichi Kawakami - Kusatsu, JP
Mitsuru Funato - Kyoto, JP
Shigeo Fujita - Kyoto, JP
Assignee:
Nichia Corporation - Tokushima
International Classification:
H01L031/0328
US Classification:
257183, 257187, 257200, 438 48, 438 60
Abstract:
The luminous efficiency of a nitride semiconductor device comprising a gallium nitride-based semiconductor layer formed on a dissimilar substrate is improved. An n-type layer formed on the substrate with a buffer layer interposed between them comprises a portion of recess-and-projection shape in section as viewed in the longitudinal direction. Active layers are formed on at least two side faces of the projection with the recess located between them. A p-type layer is formed within the recess. An insulating layer is formed on the top face of the projection, and on the bottom face of the recess. The n-type layer is provided with an n-electrode while the p-type layer is provided with a p-electrode contact layer. As viewed from the p-type layer formed within the recess in the gallium nitride-based semiconductor layer, the active layer and the n-type layer are located in an opposite relation to each other. As viewed from the side face of the recess, the active layer and the p-type layer are formed across the n-type layer.

Nitride Semiconductor Device, And Its Fabrication Process

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US Patent:
7348600, Mar 25, 2008
Filed:
Oct 20, 2003
Appl. No.:
10/687768
Inventors:
Yukio Narukawa - Anan, JP
Isamu Niki - Anan, JP
Axel Scherer - Pasadena CA, US
Koichi Okamoto - Pasadena CA, US
Yoichi Kawakami - Kusatsu-shi, Shiga 525-0029, JP
Mitsuru Funato - Kyoto-shi, Kyoto 615-8084, JP
Shigeo Fujita - Kyoto-shi, Kyoto 612-0854, JP
Assignee:
Nichia Corporation - Tokushima
California Institute of Technology - Pasadena CA
International Classification:
H01L 21/15
US Classification:
257 79, 257 94, 257103, 257E31058
Abstract:
The invention provides a nitride semiconductor light-emitting device comprising gallium nitride semiconductor layers formed on a heterogeneous substrate, wherein light emissions having different light emission wavelengths or different colors are given out of the same active layer. Recesses are formed by etching in the first electrically conductive (n) type semiconductor layer formed on a substrate with a buffer layer interposed between them. Each recess is exposed in plane orientations different from that of the major C plane. For instance, the plane orientation of the A plane is exposed. An active layer is grown and joined on the plane of this plane orientation, on the bottom of the recess and the C-plane upper surface of a non-recess portion. The second electrically conductive (p) type semiconductor layer is formed on the inner surface of the recess. With the active layer formed contiguously to the semiconductor layer in two or more plane orientations, a growth rate difference gives rise to a difference in the thickness across the quantum well (active layer), giving out light emissions having different light emission wavelength peaks or different colors.

Surface Plasmon Light Emitter Structure And Method Of Manufacture

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US Patent:
20050285128, Dec 29, 2005
Filed:
Feb 9, 2005
Appl. No.:
11/055005
Inventors:
Axel Scherer - Laguna Beach CA, US
Koichi Okamoto - Pasadena CA, US
Assignee:
California Institute of Technology - Pasadena CA
International Classification:
H01L029/22
US Classification:
257098000
Abstract:
A method (and resulting structures) for manufacturing light emitting semiconductor devices. The method includes providing a substrate comprising a surface region and forming a metal layer overlying the surface region of the substrate. In a specific embodiment, the metal layer and the surface region are characterized by a spatial spacing between the metal layer and the substrate to cause a coupling between electron-hole pairs generated in the substrate and a surface plasmon mode at an interface region between the metal layer and the surface region. Additionally, the interface region has a textured characteristic between the surface region and the metal layer. The textured characteristics causes emission of electromagnetic radiation through the surface plasmon mode or like mechanism according to a specific embodiment.
Koichi R Okamoto from Rolling Hills Estates, CA, age ~61 Get Report