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Howard Q Tran

from Westminster, CA
Age ~61
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Also known as:
Howard H Tran, Hung Quoc Tran, Quoc Tran Howard, Hung Q Tran, Tran Howard, Bee Nails
Phone and address:
15682 Grey Oaks St, Westminster, CA 92683
(714) 418-1234
Related to:
Tuan Khac Tran, 54
Connected to:
Alexandria P Tran, 53Allie T Tran, 52Amber Y Tran, 67Andrew H Tran, 53Angelique H Tran, 53Anh Tran, 58Anton D Tran, 43Augustine N Tran, 34Bea L Tran, 48Beana B Tran, 62

Howard Tran Phones & Addresses

  • 15682 Grey Oaks St, Westminster, CA 92683 (714) 418-1234 (714) 839-6944
  • Millville, NJ
  • 54 Yorkshire Village Rd, Trenton, NJ 08648 (609) 919-0563
  • Lawrenceville, NJ
  • 43 Greentree Dr, Burlington Township, NJ 08016 (609) 614-7813 (609) 747-7853
  • Burlington, NJ
  • Huntington Beach, CA
  • 43 Greentree Dr, Burlington, NJ 08016

Work

Company: Google inc Jun 2012 Position: Project / sales coordinator

Education

School / High School: University of California, Berkeley- Berkeley, CA May 2012 Specialities: Bachelor of Science in Conservation and Resource Management

Resumes

Resumes

Howard Tran Photo 1

Cofounder At Causora

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Position:
Co-founder at causora
Location:
Greater Los Angeles Area
Industry:
Internet
Work:
causora - Culver City, CA since Sep 2012
Co-founder
GSN - Santa Monica, Ca Apr 2012 - Jun 2013
Director of Interactive Development
Technicolor Nov 2009 - Apr 2012
Lead Applications Engineer
NBC Apr 2008 - Oct 2009
Flash Developer
The Buddy Group Apr 2007 - Apr 2008
Senior Developer
Education:
Devry University 2000 - 2003
BS, CIS
Honor & Awards:
Certified Scrum Master
Howard Tran Photo 2

Gambling & Casinos Professional

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Location:
Greater Los Angeles Area
Howard Tran Photo 3

Howard Tran

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Howard Tran Photo 4

Howard Tran

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Howard Tran Photo 5

Howard Tran

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Howard Tran Photo 6

Analyst At Warner Bros.

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Position:
Analyst at Warner Bros.
Location:
Greater Los Angeles Area
Industry:
Entertainment
Work:
Warner Bros.
Analyst
Howard Tran Photo 7

Regional Marketing Coordinator At Colliers International

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Location:
Orange County, California Area
Industry:
Commercial Real Estate
Howard Tran Photo 8

Howard Tran Santa Clara, CA

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Work:
Google Inc

Jun 2012 to 2000
Project / Sales Coordinator
Pi Kappa Phi Fraternity

2010 to 2012
Kelly's Collection
Los Angeles, CA
2004 to 2008
Customer Sales Representative
Education:
University of California, Berkeley
Berkeley, CA
May 2012
Bachelor of Science in Conservation and Resource Management

Business Records

Name / Title
Company / Classification
Phones & Addresses
Howard Tran
Xt 66011
Broadcom Corporation
Semiconductors and Related Devices
5300 California Ave, Irvine, CA 92617
Howard Tran
Xt 66011
Broadcom Corporation
Semiconductors and Related Devices
5300 California Ave, Irvine, CA 92617
Howard Tran
6th and Ximeno Associates, A California Limited Partnership
6865 Washington Blvd, Montebello, CA 90640
Howard Tran
President
Stadium Way Development Inc
3033 Wallingford Rd, Pasadena, CA 91107
Howard Tran
President
TRANPANCO, INC
6865 E Washington Blvd, Montebello, CA 90640
Howard Tran
President
COSMOS (U.S.A.) CHEMICAL, INC
513 S Atlantic Blvd #618, Monterey Park, CA 91754

Publications

Us Patents

Efficient Metric Memory Configuration For A Viterbi Decoder

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US Patent:
6438181, Aug 20, 2002
Filed:
May 28, 1999
Appl. No.:
09/321682
Inventors:
Jyoti Setlur - Irvine CA
Howard Tran - Downey CA
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
International Classification:
H04L 2706
US Classification:
375341, 375262, 714795, 704242, 370342
Abstract:
An apparatus and method thereof for storing and retrieving information in a Viterbi decoder. The apparatus includes a bus and a branch metric generator unit coupled to the bus. The branch metric generator unit generates metrics by measuring a difference between an encoded data bit and an expected data bit calculated using a convolutional code. A memory unit is also coupled to the bus. The memory unit includes a first register and a second register for storing the metrics. A parity bit is used to indicate a register for storing the metrics. In a first stage of the Viterbi decoder, a metric for a first state is stored at a first address in the first register and a metric for a second state is stored at a second address in the second register. The first state and the second state each branch to a third state and a fourth state in a trellis code of the Viterbi decoder.

Method And System Of Initializing State Metrics For Traffic, Paging, And Sync Channels To Enhance Viterbi Decoder Performance

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US Patent:
6542492, Apr 1, 2003
Filed:
May 28, 1999
Appl. No.:
09/322293
Inventors:
Howard Tran - Downey CA
Jyoti Setlur - Irvine CA
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
International Classification:
G21C 2300
US Classification:
370342, 370335, 370329, 370350, 370341, 455452, 455458, 714795
Abstract:
A method and system of initializing state metrics for traffic, paging, and sync channels to enhance Viterbi decoder performance. Specifically, one embodiment of the present invention includes a common circuit adapted for initializing state metric data of a traffic channel, a paging channel, and a sync channel within a Code Division Multiple Access (CDMA) system without compromising performance of any channel. The common circuit comprises a multiplexer stage coupled to receive a first signal and a second signal. Furthermore, the common circuit comprises a logic stage coupled to receive a plurality of signals. Additionally, the logic stage is also coupled to the multiplexer stage. As such, the multiplexer stage and the logic stage are adapted to initialize state metric data of any one of a traffic channel, a paging channel, and a sync channel within a Code Division Multiple Access (CDMA) system. It is appreciated that the common circuit does not compromise performance of any one of the traffic channel, the paging channel, and the sync channel.

Efficient Apparatus And Method For Generating A Trellis Code From A Shared State Counter

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US Patent:
6587519, Jul 1, 2003
Filed:
May 28, 1999
Appl. No.:
09/322703
Inventors:
Howard Tran - Downey CA
Jyoti Setlur - Irvine CA
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
International Classification:
H03D 100
US Classification:
375341
Abstract:
An apparatus and method thereof for decoding a stream of binary digits encoded according to a convolutional code. The apparatus includes a bus, a N-bit counter coupled to the bus, and a trellis code generator coupled to the bit counter. The bit counter is adapted to generate a sequence of N binary bits. The trellis code generator includes a first logical gate and a second logical gate. The trellis code generator is adapted to specify a first set of binary digits from the sequence of N binary bits and to pass the first set of binary digits through the first logical gate to produce a first binary value. The trellis code generator is also adapted to specify a second set of binary digits from the sequence of N bits and to pass the second set of binary digits through the second logical gate to produce a second binary value. The first set of binary digits are particularly specified so that the first binary value emulates a first value of a first encoded bit that would have been determined using the convolutional code. Similarly, the second set of binary digits is specified so that the second binary value emulates a first value of a second encoded bit that would have been determined using the convolutional code.
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Howard Q Tran from Westminster, CA, age ~61 Get Report