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Hoai T Tran

from San Jose, CA
Age ~50
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Also known as:
Thu Thanh Tran, Thu Ha Tran, Tammy Thanh Tran, Thanh H Tran, Ha T Tran, Huong T Tran, Thu Tran Ha, Tran Hoai
Phone and address:
3242 Delta Rd, San Jose, CA 95135
(408) 223-1484
Related to:
Allison Luong
Connected to:
Alexandria P Tran, 53Allie T Tran, 52Amber Y Tran, 67Andrew H Tran, 53Angelique H Tran, 53Anh Tran, 58Anton D Tran, 43Augustine N Tran, 34Bea L Tran, 48Beana B Tran, 62

Hoai Tran Phones & Addresses

  • 3242 Delta Rd, San Jose, CA 95135 (408) 223-1484
  • Santa Clara, CA

Professional Records

License Records

Hoai Tran

License #:
3025102 - Expired
Issued Date:
Feb 20, 1999
Expiration Date:
Sep 3, 2008
Type:
Manicurist Type 3

Resumes

Resumes

Hoai Tran Photo 1

Hoai Tran

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Education:
Foreign Trade University
Skills:
Management
Leadership
Microsoft Excel
Research
Microsoft Office
Training
Photoshop
Powerpoint
Microsoft Word
Sales
Hoai Tran Photo 2

Server Engineer

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Location:
9573 High Cliffe St, Littleton, CO 80129
Industry:
Financial Services
Work:
Computershare
Server Engineer
Interests:
Sports
Electronics
Languages:
Korean
Hoai Tran Photo 3

Hoai Tran

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Hoai Tran Photo 4

Hoai Tran

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Hoai Tran Photo 5

Hoai Tran

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Hoai Tran Photo 6

Hoai Tran

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Skills:
Leadership
Hoai Tran Photo 7

Hoai Tran

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Hoai Tran
President
KL TOP MUSIC, INC
1111 Story Rd STE 1088, San Jose, CA 95122

Publications

Us Patents

Array Machine Context Data Memory

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US Patent:
7424571, Sep 9, 2008
Filed:
Jul 13, 2005
Appl. No.:
11/181611
Inventors:
Somsubhra Sikdar - San Jose CA, US
Kevin Jerome Rowett - Cupertino CA, US
Hoai V. Tran - Gilroy CA, US
Jonathan Sweedler - Los Gatos CA, US
Komal Rathi - Sunnyvale CA, US
Mike Davoudi - San Jose CA, US
Assignee:
Gigafin Networks, Inc. - Cupertino CA
International Classification:
G06F 12/02
US Classification:
711108, 711101, 710 52, 710 56
Abstract:
A device performs lookup functions for a semantic processing unit. The device comprises a plurality of interface circuits for receiving data operation requests from the semantic processing unit. The device comprises a buffer for allocating an interface circuit to a semantic processing unit having a data operation request. A selection circuit, coupled between the plurality of interface circuits and a memory unit, selects an allocated circuit for accessing the memory unit to process the data operation request.

Arbiter For Array Machine Context Data Memory

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US Patent:
7451268, Nov 11, 2008
Filed:
Jul 13, 2005
Appl. No.:
11/181598
Inventors:
Somsubhra Sikdar - San Jose CA, US
Kevin Jerome Rowett - Cupertino CA, US
Hoai V. Tran - Gilroy CA, US
Jonathan Sweedler - Los Gatos CA, US
Komal Rathi - Sunnyvale CA, US
Mike Davoudi - San Jose CA, US
Assignee:
Gigafin Networks, Inc. - Cupertino CA
International Classification:
G06F 12/02
US Classification:
711108, 710 52, 710 56
Abstract:
A device comprises a plurality of interface circuits configured for communicating between a semantic processing unit and a memory and a selection circuit for selecting an interface circuit allocated to a semantic processing unit for processing a data operation request in the memory.

Contextual Memory Interface For Network Processor

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US Patent:
20060020756, Jan 26, 2006
Filed:
Jul 13, 2005
Appl. No.:
11/181117
Inventors:
Hoai Tran - Gilroy CA, US
Kevin Rowett - Cupertino CA, US
Somsubhra Sikdar - San Jose CA, US
Jonathan Sweedler - Los Gatos CA, US
Caveh Jalali - Redwood City CA, US
International Classification:
G06F 12/00
US Classification:
711119000, 711158000
Abstract:
A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache used for controlling cache operations for different processing devices accessing the same data, and a streaming cache configured for large packet data memory accesses. An arbiter may be used for arbitrating requests by the multiple different caches for accessing the main memory.

Lookup Interface For Array Machine Context Data Memory

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US Patent:
20060026377, Feb 2, 2006
Filed:
Jul 13, 2005
Appl. No.:
11/181599
Inventors:
Somsubhra Sikdar - San Jose CA, US
Kevin Rowett - Cupertino CA, US
Hoai Tran - Gilroy CA, US
Jonathan Sweedler - Los Gatos CA, US
Komal Rathi - Sunnyvale CA, US
Mike Davoudi - San Jose CA, US
International Classification:
G06F 12/00
US Classification:
711170000, 711118000
Abstract:
A device comprises a plurality of interface circuits for communicating between a semantic processor and a memory. Each interface circuit is configured for receiving lookup requests from the semantic processor. The device further comprises a buffer for allocating an interface circuit, if available, to the semantic processor. The allocated interface circuit is selected to access the memory for processing the lookup request.
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Hoai T Tran from San Jose, CA, age ~50 Get Report