Fred Hartnett

6437587, Aug 20, 2002

Nov 4, 1999

09/434195

Fred Hartnett - Plano TX
Terry Conner - Garland TX

Agilent Technologies, Inc. - Palo Alto CA

G01R 3102

324755, 3241581, 324754

A test fixture for performing in-circuit testing of a printed circuit assembly may comprise a board having a front surface and a back surface. A probe assembly also having a front surface and a back surface is mounted to the board so that the back surface of the probe assembly is adjacent the front surface of the board. The probe assembly includes at least one front surface contact pad positioned on the front surface of the probe assembly that is electrically connected to at least one back surface contact pad positioned on the back surface of the probe assembly. A first board pad positioned on the front surface of the board makes electrical contact with the back surface contact pad on the back surface of the probe assembly. An electrical conductor operatively associated with the board electrically connects the board pad to an input/output pad that is also provided on the board.

7590909, Sep 15, 2009

Aug 24, 2005

11/210415

Fred Hartnett - Plano TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

G01R 31/28

714727, 714734

An in-circuit testing system comprises an integrated circuit having a tri-state control pin used for inducing a tri-state mode in the integrated circuit during a scan test of the integrated circuit for controlling a time period for outputting a value associated with the scan test.

8327202, Dec 4, 2012

Jul 13, 2005

11/180429

Fred Hartnett - Plano TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

G01R 31/28

714726, 714727, 714729

A scan system comprises a scan engine adapted to receive a scan request from a host system for performing a scan test on a system-under-test. The scan engine comprises dedicated logic where a state of the dedicated logic is adapted to control processing of the scan request on the system-under-test.

8621304, Dec 31, 2013

Oct 7, 2004

10/960590

Fred Hartnett - Plano TX, US
Robert McFarland - Murphy TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

G01R 31/28

714733

An integrated circuit comprises random logic communicatively coupled to a non-scannable memory array. The integrated circuit also comprises a built-in self-test (BIST) controller adapted to apply test data to the random logic and propagate the test data through the random logic to test the memory array.

20050083071, Apr 21, 2005

Oct 16, 2003

10/686699

Fred Hartnett - Plano TX, US
Kin Tam - Elk Grove CA, US

G01R031/02

324754000

An electronic circuit assembly test apparatus comprises a support member having a plurality of probes each adapted to contact a corresponding test area of an electronic circuit assembly. The apparatus also comprises a probe assembly coupled to the support member. The probe assembly also comprises a plurality of probes where a spacing density of the probes of the probe assembly is greater than a spacing density of the probes of the support member.

51596962, Oct 27, 1992

Jul 27, 1990

7/558813

Fred J. Hartnett - Dallas TX

Microelectronics and Computer Technology Corporation - Austin TX

H03K 2102

377 55

Two cascaded eight-bit maskable counters (62) and (64) provide a sixteen-bit output, for instance, to a digital-to-analog converter (10). Each of the counters (62) and (64) is a maskable counter that is operable to mask off a programmable number of the least significant bits therein. The next adjacent bit thereto comprises a virtual least significant bit. During the counting operation, the count is initiated at the virtual least significant bit such that the virtual least significant bit is clocked for each counting cycle. An initial value is first loaded into the counter (62) and (64) on a data bus (74). Thereafter, masked data is loaded into the counters (62) and (64) on the same data bus (74) to define the ones of the least significant bits that are masked off. In such a manner, the overall resolution of the counter can be varied without varying the clock rate to the counter. By masking off the bits, the count is automatically incremented by a value equal to that represented by the masked off bits for each cycle of the clock input to the counter.