Dwight A Patterson

Electrical Engineering Adjunct Instructor at ITT Technical Institute

Richardson, Texas

Semiconductors

ITT Technical Institute - Richardson, TX since Sep 2011
Electrical Engineering Adjunct Instructor
Texas Instruments - Dallas, TX Aug 2011 - Nov 2011
ASIC Design Engineer
Rockwell Collins - Richardson, TX Apr 2011 - Jul 2011
Digital Design Engineer
Samsung Telecommunications America Aug 2004 - Feb 2009
Digital Chip Design Engineer
CoreApps Oct 2002 - Aug 2004
Manager/Lead Design Services Engineer

Mississippi State University 1990 - 1991
Masters, Electrical Engineering Mississippi State University 1985 - 1990
BS, Electrical Engineering and Mathematics

ASIC
FPGA
RTL Design
Digital Design
Digital Synthesis
Digital Verification
Self-checking Testbench creation
Static Timing Analysis
Semiconductor Design
Xilinx
VHDL
Verilog
Front-end Development and Back-end Interface
Pre-sales Technical Support
Post-sales Technical Support
Design Documentation
Synopsys
Cadence
Mentor Graphics
EDA
Integrated Circuit Design
Pre-sales
RTL design
Semiconductors

SKILLS: Over 20 years: front-end design, self-checking Verilog/VHDL testbench verification, back-end support. First-pass silicon successes for high-speed, low-power, digital and mixed RFIC chip design flows. Verilog and VHDL RTL design for semiconductor chips (both ASICs and FPGAs). Created an unique EDA synthesis process to speed up digital netlists to GHz clock speeds. Root cause analysis in digital chip designs. Chip specification documentation creation. Created Synopsys ASIC and Xilinx FPGA design checkers for high-quality development. Synopsys Design Compiler, Cadence Encounter RTL Compiler, Xilinx ISE for synthesis. Synopsys Power Compiler with SAIF for power optimization during synthesis and power analysis post-synthesis. Synopsys TetraMAX for ATPG. Synopsys PrimeTime-SI for static timing analysis. Cadence AMS training for analog/digital co-simulation. NCSim, QuestaSim, ModelSim, VCS, NC-Verilog, Verilog-XL, SureCov, Signalscan. Xilinx CoreGen for DDS generation.

American Sign Language

United States

Math Teacher/Golf Coach at Heritage High School

Vancouver, Washington

Primary/Secondary Education

Washington State University 2004 - 2009
Principal Certification University of Portland 1989 - 1992
Masters of Education George Fox University 1981 - 1985
Bachelor of Science, Mathematics

Senior Architect/Team Lead Developer at Eton Park

Greater New York City Area

Financial Services

Eton Park since Jun 2008
Senior Architect/Team Lead Developer
Drake Management LLC 2003 - Jun 2008
Director, Head of Trading Systems Development
BlackRock 1998 - 2003
Associate, Trading Systems Group
BlackRock Financial Management 1998 - 2003
Associate, Trading Systems