David Everette Mccall

62790730, Aug 21, 2001

Sep 30, 1999

9/410137

David E. McCracken - San Francisco CA
David L. McCall - Eau Claire WI

Silicon Graphics, Inc. - Mountain View CA

G06F 1200

711105

A configurable synchronizer (10) for DDR-SDRAM (12) is provided that includes a strobe select module (40) operable to receive a memory select signal (106) and to pass strobe signals (20, 30) from one or more DDR-SDRAMs (16, 18) to a number of synchronizer circuits (44) corresponding to data signals (17) passed in parallel by each DDR-SDRAM as indicated by the memory select signal (106). A rising edge latch (174) receives a rising edge data signal (170) and latches the rising edge data signal (170) through the rising edge latch (174) on a rising edge of the strobe signal (152). A falling edge latch (176) receives a falling edge data signal (172) and latches the falling edge data signal (172) through the falling edge latch (176) on a falling edge of the strobe signal (152). A data signal selector (180) receives a data order control signal (195) and forwards the rising edge data signal (170) from the rising edge latch (174) to an intermediate output (196) on either a rising edge of a memory clock cycle (193) or a falling edge of a memory clock cycle (193) followed by forwarding the falling edge data signal (172) from the falling edge latch (176) to the intermediate output (196) on an opposite edge of the memory clock cycle (193) in response to the data order control signal (195). An output latch (202) receives the intermediate output (196) and latches the intermediate output (196) through the output latch (202) to an output signal (154) on each core clock cycle (190).