Carlos M Fernandez

D648095, Nov 1, 2011

Nov 11, 2010

29/378918

Carlos F. Fernandez - Miami Beach FL, US
Diego Lorenzo - Miami Beach FL, US

9900

D99 34

20150356498, Dec 10, 2015

Jun 8, 2015

14/733113

Andres E. Casanova - AVENTURA FL, US
Carlos Damian Fernandez - Walnut CA, US

G06Q 10/08
G07B 15/06

Managing parking is carried out by associating an electronic tag with a vehicle, each tag configured to either receive, transmit, or both receive and transmit information at a low frequency using magnetic induction. A base station located in each parking space is likewise configured to either receive, transmit, or both receive and transmit information at a low frequency using magnetic induction. Either the tag or the base station will communicate identification information of both the tag and the base station to one or more servers, where parking can be managed. Communication with the server can be carried out in part using a publicly available radio frequency over a wide area network, such as one of the SigFox, LoRaWAN, or WEIGHTLESS protocols.

20150278005, Oct 1, 2015

Jun 23, 2014

14/312327

- Armonk NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

G06F 11/07

A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.

20150278086, Oct 1, 2015

Mar 27, 2014

14/227187

- Armonk NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

International Business Machines Corporation - Armonk NY

G06F 12/02
G06F 11/10

A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.

20150213853, Jul 30, 2015

Jan 30, 2014

14/168102

- ARMONK NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

G11C 7/10

A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.

20150213854, Jul 30, 2015

Jun 20, 2014

14/310717

- Armonk NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

G11C 7/10

A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.

20150127898, May 7, 2015

Nov 7, 2013

14/074117

- Armonk NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
William P. Hovis - Rochester MN, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

International Business Machines Corporation - Armonk NY

G11C 11/406

711106

A refresh command is communicated to a memory device to initiate an interruptible refresh which contains multiple segment refreshes separated by interrupt boundaries. A command is communicated to the memory device before execution of a segment refresh and the segment refresh is delayed at an interrupt boundary. Alternatively, a first number of commands in a queue is determined. A first number of segment refreshes to execute is determined based on the first number of commands. The first number of segment refreshes to execute is communicated to the memory device to cause execution of the first number of segment refreshes. A second number of commands in the queue is determined. A second number of segment refreshes to execute is determined based on the second number of commands. The second number of segment refreshes to execute is communicated to the memory device to cause execution of the second number of segment refreshes.

20150127899, May 7, 2015

Nov 7, 2013

14/074171

- Armonk NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
William P. Hovis - Rochester MN, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

International Business Machines Corporation - Armonk NY

G11C 11/406

711106

A refresh command is received from a memory controller. An interruptible refresh containing multiple segment refreshes is initiated. The segment refreshes are separated by interrupt boundaries. A command is received before execution of a segment refresh. The first command is executed and execution of the first segment refresh is delayed at a first interrupt boundary. Alternatively, a first number of segment refreshes to execute is received from a memory controller. The received first number of segment refreshes is executed. A second number of segment refreshes to execute is received from a memory controller. The received second number of segment refreshes is executed. No segment refreshes are executed between the execution of the first number of segment refreshes and the execution of the second number of segment refreshes.