Anthony Miller

59906995, Nov 23, 1999

Jan 16, 1996

8/587088

Anthony C. Miller - Gilbert AZ
Wayne M. Needham - Gilbert AZ

Intel Corporation - Santa Clara CA

G01R 3126

324769

A method for detecting open circuits in a semiconductor device, more specifically in a static CMOS device. A device to be tested is powered-up and the clock on the device is stopped so that the device enters a quiescent state. Once the device has reached a quiescent state a first current is measured and after a specified period of time a second current is also measured. The first current and the second current are then compared to determine if there is a defect, i. e. an open circuit, in the device. The determination as to whether or not a device is defective is based upon the difference between the first and second current measurements.

62083929, Mar 27, 2001

Feb 26, 1999

9/258226

Anthony C. Miller - Gilbert AZ
Kannan Raj - Chandler AZ

Intel Corporation - Santa Clara CA

G02F1/1333;1/1339

349 84

An electro-optical device may be defined using metallic standoffs between a top plate and a substrate, such as a silicon substrate in a liquid crystal on silicon (LCOS) technology. In one embodiment, the metallic standoffs may be formed from a metal layer, such as metal four layer, above the metal layer used to form the metal pixel mirrors. In this way, relatively constant and uniform cell thicknesses may be achieved without significantly increasing the processing overhead.

58894080, Mar 30, 1999

Jun 27, 1996

8/670545

Anthony C. Miller - Gilbert AZ

Intel Corporation - Santa Clara CA

G01R 3128

324765

A method for IDDQ testing to detect defects in a semiconductor device in the presence of a high background leakage current. In one embodiment at least a portion of a semiconductor device is biased and a first quiescent current measurement is taken. The portion of the semiconductor device that was biased is then unbiased and a second quiescent current measurement is taken. The first and second quiescent currents are then compared to determine if a defect exists in that portion of the semiconductor device.

62155342, Apr 10, 2001

Mar 31, 1999

9/283337

Kannan Raj - Chandler AZ
Oleg Rashkovskiy - Cupertino CA
Anthony C. Miller - Gilbert AZ

Intel Corporation - Santa Clara CA

G02F 11333
G02F 11343
G02F 11339

349 84

An electro-optical device may include two pairs of electrodes which apply electric fields oriented at an angle with respect to one another. In this way, a second electric field may be used to create an alignment effect in the electro-optic material which normally is achieved using specially prepared alignment structures. The need for the alignment structures may be reduced or eliminated. The second electric field may be applied, for example, using metallic standoffs which space a top plate from a lower substrate and define a region for the electro-optic material. In this way, in large arrays, the electric field may be applied from a plurality of points improving the uniformity of the applied electric field. In smaller arrays, the field may be applied, for example, using peripheral electrodes.

62784285, Aug 21, 2001

Mar 24, 1999

9/275615

Ronald D. Smith - Phoenix AZ
Anthony C. Miller - Gilbert AZ

Intel Corporation - Santa Clara CA

G09G 336

345 92

A system includes an array of pixel cells, column lines, storage elements and decoding circuitry. The pixel cells are arranged in rows and columns and the column lines are associated with the column pixel cells. The storage elements are associated with a row of the pixel cells. The decoding circuitry is adapted to storage charges on the column lines and after the storage, transfer the charges from the column lines to the storage elements.

62396056, May 29, 2001

Sep 29, 1998

9/162912

Anthony C. Miller - Gilbert AZ

Intel Corporation - Santa Clara CA

G01R 3100
G01R 3128

324765

A method for IDDQ testing to detect defects in a semiconductor device in the presence of a high background leakage current. At least a portion of a semiconductor device is biased and a first quiescent current measurement is taken. The measured portion of the semiconductor device is then unbiased and a second quiescent current measurement is taken. The first and second quiescent currents are then compared to determine if a defect exists in the tested portion of the semiconductor device.

62396064, May 29, 2001

Sep 29, 1998

9/163592

Anthony C. Miller - Gilbert AZ

Intel Corporation - Santa Clara CA

G01R 3128

324765

A method for IDDQ testing to detect defects in a semiconductor integrated circuit in the presence of a high background leakage current is disclosed. In one embodiment of the present invention at least a portion of the semiconductor device is biased and first, second and third quiescent currents are measured and the currents are then compared. A defect in the circuit will show up as a high quiescent current for one or more of the biasing conditions. In a practical device many test patterns are required, for instance 200 patterns may be necessary to reveal defects. Additionally, the delta in current which is sought to detect the defect may need to be repeated several times to assure its detection.